Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Pronita Mehrotra

dblp:91/381 · DBLP profile ↗
← Back
3ranked-venue papers
2as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorComputer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Internet architecture and protocols · 56% Optical networks · 44%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet architecture and protocols
network interface card
0.012004
FPGA implementation of a high speed network interface card for optical burst switched networks · FPGA 2004
Optical networks › optical switching
optical burst switching
0.012004
FPGA implementation of a high speed network interface card for optical burst switched networks · FPGA 2004
Internet architecture and protocols
signaling protocol
0.012004
FPGA implementation of a high speed network interface card for optical burst switched networks · FPGA 2004
Reconfigurable computing and FPGAs
FPGA implementation
0.012004
FPGA implementation of a high speed network interface card for optical burst switched networks · FPGA 2004

Methods — techniques the papers use, named apart from their topics

FPGA transceiver · 0.1
YearPublicationVenuePosition
2004 A High Speed Network Interface Card for Optical Burst Switched Networks
abstract
Optical burst switching (OBS) is emerging as an optical networking technology combining best of the features of optical circuit-switching technology and optical packet-switching technology. This paper discusses architecture and hardware implementation of a network interface card (NIC) for an OBS network. The NIC implements a specific low-latency signaling protocol just-in-time (JlT) for OBS networks. This NIC can handle data streams up to 1 Gbps. Average OBS JIT signaling message processing time with this NIC is on the order of 1 microsecond. This is the first JIT OBS NIC implementation known to the authors. Complementary efforts are on-going to develop other elements for the OBS network.
Mrugendra Singhai, Pronita Mehrotra, Patrick Hamilton, Mike Pratt, Mark Cassada, Daniel S. Stevenson
BROADNETS2
2004 FPGA implementation of a high speed network interface card for optical burst switched networks
abstract
Current generation of FPGAs with integrated high-speed transceivers provide a useful tool for prototyping various networking applications. We discuss a case study in developing a high-speed network interface card (NIC) for communication networks. The NIC implements a low-latency signaling protocol called Just-in-Time (JIT) for Optical Burst Switched networks. The main processing engine inside the FPGA runs at 62.5MHz and can handle data streams up to 1Gbps. The NIC utilizes the FPGA's gigabit transceiver cores, standard PCS/PMA and MAC layers and uses an optical front-end card to transmit data optically on specific wavelengths. The JIT engine in the NIC processes three kinds of messages - messages from the host, the network and internal timing messages associated with various timer events. The engine implements layer 3 functions typically implemented in software - like generating signaling messages and maintaining all active connections. This allows very fast setup and teardown of connections than otherwise possible.
Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton
FPGA1
2002 Binary search schemes for fast IP lookups
abstract
Route lookup is becoming a very challenging problem due to the increasing size of routing tables. To determine the outgoing port for a given address, the longest matching prefix among all the prefixes, needs to be determined. This makes the task of searching in a large database quite difficult. Our paper describes binary search schemes that allow fast address lookups. Binary search can be performed on the number of entries or on the number of mutually disjoint prefixes. Lookups can be performed in O(N) time, where N is number of entries and the amount of memory required to store the binary database is also O(N). These schemes scale very well with both large databases and for longer addresses (as in IPv6).
Pronita Mehrotra, Paul D. Franzon
GLOBECOM1