This paper presents a novel method of reducing the spurious signal content in a digitally synthesized sine wave at the output of a numerically controlled oscillator (NCO). The proposed method uses a linear approximation subsystem with a reduced size look-up table (LUT). Two NCO architectures are considered. Architecture 0 - which is the standard - in which the accumulator word length is longer than the LUT address word, is compared with Architecture 1, where the accumulator bits beyond the LUT address space are used for the linear approximation of the value in between the entries of the LUT. Analysis of both architectures demonstrates that the spurious free dynamic range (SFDR) in Architecture 1 equates to 12 dBc per bit of the address space of the LUT as opposed to 6 dBc for Architecture 0. The system was implemented and tested using the Xilinx Spartan 3 platform.

Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore we present a mapping algorithm which ldquocompilesrdquo the parity-check matrix of the desired LDPC code. This concept allows adaption of the decoder controller to different LDPC codes without requiring a new synthesis run. We implemented the proposed decoder on a XILINX XC4LX160 FPGA and give bit error rates to verify design and mapping algorithm. In contrast to previously presented flexible implementations our design is able to decode LDPC codes of 30 times longer codeword lengths up toN = 65, 000.

This paper presents a non-monolithic top-down reconfigurable multiplier suitable for embedding in an FPGA structure. It is constructed of four individual partitions that can operate as separate multipliers but also concatenate to form a superior multiplier with increased precision and sign handling ability. The number of possible operation modes is limited in order to keep the reconfiguration overhead low. A small set of control signals determines behavior and mode selection. Inactive partitions are disconnected from the supply to save power. EMMA (Embedded Multi-precision Multiplier Array) can compute signed twopsilas complement numbers at up to 32 times 16-bit precision when all partitions are active and concatenated, or up to four separate 16 times 8-bit multiplications running simultaneously.

As hardware synthesis tries to go behavioral, system designers tend to neglect low level optimizations, e.g., retiming or resources reuse. However, complex architectures such as highly parallel sorter cores cannot be directly packed into standard devices by the electronic design automation (EDA) tools and often needs fundamental rethinking. Therefore this paper resumes a cost study of the hardware realization of a recurrent parameterizable N-sorter based on Batcher's bitonic algorithm and shows how to recombine different network sizes by preserving data throughput. With the time complexity of the original bitonic sorter, the recurrent architecture yields a lower area complexity by reducing the communication within the network and minimizes the cost in terms of hardware resources. Furthermore, the validity domain of internal architectural parameter combinations demonstrate the existence of an optimal area-throughput trade-off for very large scale integration (VLSI) models based on field programmable gate array (FPGA) synthesis, as well as a full scalability of the highly parallel sorting scheme

A conversion flow from a Xilinx Virtex-II Pro FPGA to a Zelix MPGA has been presented. The Zelix MPGA has a predefined regular interconnect. Experimental investigations (Feredas et al.,2006) indicate that the FPGA interconnect has more delay than the proposed MPGA. With better timing closure, studies with the MPGA router shows that a relaxed routing is area prohibitive. Timing integrity seems to be obtainable with high security

Power consumption is a limiting factor to FPGA viablility in applications such as portable devices. LUT-based mask-programmable gate-arrays (LUT-based MPGAs) are alternatives to reach the fast turnaround times of an FPGA with low design cost and low power consumption. A LUT-based MPGA preserves the same logic-structure of a LUT-based FPGA. Unlike FPGAs, the programmable configuration and interconnect is mask-programmable. This paper describes a methodology to estimate power consumption in a LUT-based MPGA. The proposed methodology uses a gate-power estimation tool. The dynamic and static powers of the basic-gates are modeled in a library. The interconnect is easily modeled because the programmable metal-masks are predefined. A comparison with a transistor-level simulation shows an average difference of 20% with the final power result. The experiments show that the major contributor of the power consumption in the MPGA is the clock network. Power results on MPGAs and FPGAs are compared. The dynamic power consumption in the logic is reduced by 73%. The major power reduction is observed in the interconnects. Static power consumption in the LUT-based MPGA is insignificant compared its dynamic power consumption

This paper presents two LUT-based MPGA architectures. The first MPGA architecture preserves the logic and the hierarchical routing interconnect scheme of an FPGA. The second MPGA architecture has a new regular routing interconnect scheme. Our experiments reveal an average area reduction of 97% in the second architecture compared to the first architecture and 81% in respect of an FPGA. The shrinking factor yields a reduction of 94% in the interconnect delay and 75% in the effective capacitance of a one-length wire. A study in one industrial design shows that the first architecture and the FPGA have 40% of more total wire-length. The second architecture has a potential reduction in dynamic power consumption.

Due to the enormous increase in the stored digital contents, search and retrieval functionalities are necessary in multimedia systems. Though processor speed for standard PCs (Personal Computers) is experiencing an almost exponential growth, the memory subsystem handicapped by lower frequencies and a physical I/O (Input/Output) limitation reflects the bottleneck of common computer architectures. As a result, many applications such as database management systems remain so dependent on memory throughput that increases in CPU (Central Processing Unit) speeds are no longer helpful. Because average bandwidth is crucial for system performance, our research has focused especially on techniques for efficient storage and retrieval of multimedia data. This paper presents the realization of a hardware database search engine based on an associative access method for textual information retrieval. It reveals the internal architecture of the system and compares the results of our hardware prototype with the software solution

Two single-ended and one fully differential high-frequency BiCMOS operational amplifiers for switched-capacitor video-applications are presented. The amplifiers feature a folded cascode structure with current sources as output loads. For the single-ended amplifiers the current mirroring is accomplished with bipolar transistors at the output of the differential pair. The common-mode feedback circuitry of the differential amplifier uses two nested differential input pairs. The amplifiers are integrated in an analog 1 /spl mu/m BiCMOS process,with an active die area of 0.72 mm/sup 2/ and 0.96 mm/sup 2/ for the single-ended and the fully differential amplifier, respectively. For all amplifiers a dc-gain of 68 dB and a unity gain frequency greater than 200 MHz was obtained.>

If a CCD low-pass filter is used for antialiasing, a higher data rate is necessary at the input compared to the output. This difference in the data rate is used to increase the signal-to-noise ratio. By adding a given number of consecutive charge packets at the output stage, the output data rate can be reduced until the Nyquist theorem for the output signal is violated. By summing up those charge packets, the signal is added arithmetically whereas the noise, not being correlated, is added geometrically. This results in an improvement of the S/N ratio equal to the number of charge packets added.