Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning.

Heart activity can be monitored by means of ElectroCardioGram (ECG) measure which is widely used to detect heart diseases due to its non-invasive nature. Trained cardiologists can detect anomalies by visual inspecting recordings of the ECG signals. However, arrhythmias occur intermittently especially in early stages and therefore they can be missed in routine check recordings. We propose a hardware setup that enables the always-on monitoring of ECG signals into wearables. The system exploits a fully event-driven approach for carrying arrhythmia detection and classification employing a bio-inspired spiking neural network. The two staged Spiking Neural Network (SNN) topology comprises a recurrent network of spiking neurons whose output is classified by a cluster of Leaky integrate-and-fire (LIF) neurons that have been supervisely trained to distinguish 17 types of cardiac patterns. We introduce a method for compressing ECG signals into a stream of asynchronous digital events that are used to stimulate the recurrent SNN. Using ablative analysis, we demonstrate the impact of the recurrent SNN and we show an overall classification accuracy of 95% on the PhysioNet Arrhythmia Database provided by the Massachusetts Institute of Technology and Beth Israel Hospital (MIT/BIH). The proposed system has been implemented on an event-driven mixed-signal analog/digital neuromorphic processor. This work contributes to the realization of an energy-efficient, wearable, and accurate multi-class ECG classification system.

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer paradigms. Nevertheless, the lack of modularity and poor connectivity shown by traditional neuron interconnect implementations based on shared bus topologies is prohibiting scalable hardware implementations of SNNs. This paper presents a novel hierarchical network-on-chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture incorporates a spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Analytical results show the scalability of the proposed H-NoC approach under different scenarios, while simulation and synthesis analysis using 65-nm CMOS technology demonstrate high-throughput, low-cost area, and power consumption per cluster, respectively.

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for SNN hardware which addresses the scalability issue by creating a 3-dimensional array of clusters of neurons with a hierarchical structure of low and high-level routers. The H-NoC architecture also incorporates a spike traffic compression technique to exploit SNN traffic patterns, thus reducing traffic overhead and improving throughput on the network. In addition, adaptive routing capabilities between clusters balance local and global traffic loads to sustain throughput under bursting activity. Simulation results show a high throughput per cluster (3.33×109spikes/second), and synthesis results using 65-nm CMOS technology demonstrate low cost area (0.587mm2) and power consumption (13.16mW @100MHz) for a single cluster of 400 neurons, which outperforms existing SNN hardware strategies.