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Prashant Aggarwal

dblp:93/9861 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 1 first-authorTheory of computation · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
coverage-driven verification		 0.112011
Using Coverage to Deploy Formal Verification in a Simulation World · CAV 2011
Electronic design automation › hardware verification and test
formal verification		 0.112011
Using Coverage to Deploy Formal Verification in a Simulation World · CAV 2011
Electronic design automation › hardware verification and test
hardware verification		 0.112011
Using Coverage to Deploy Formal Verification in a Simulation World · CAV 2011
Electronic design automation › hardware verification and test › functional verification
simulation-based verification		 0.012011
Using Coverage to Deploy Formal Verification in a Simulation World · CAV 2011

Methods — techniques the papers use, named apart from their topics

coverage analysis · 0.1
YearPublicationVenuePosition
2011 Using Coverage to Deploy Formal Verification in a Simulation World
abstract
Formal verification technology has today advanced to the stage that it can complement or replace simulation effort for selected hardware designs. Yet the completion of a formal verification effort is rarely a requirement for hardware tapeout. Simulation remains the primary verification methodology, and means of deciding when verification is complete. In this paper we discuss how formal verification can be deployed using simulation-based coverage in a simulation-based verification schedule.
Vigyan Singhal, Prashant Aggarwal
 CAV2
2011 Planning for end-to-end formal using simulation-based coverage: invited tutorial
Prashant Aggarwal, Darrow Chu, Vijay Kadamby, Vigyan Singhal
 FMCAD1