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Satrajit Gupta

dblp:94/144 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.012004
CHIME: coupled hierarchical inductance model evaluation · DAC 2004
Electronic design automation › interconnect modeling
inductance modeling
0.012004
CHIME: coupled hierarchical inductance model evaluation · DAC 2004
Electronic design automation › interconnect modeling
interconnect parasitic modeling
0.012004
CHIME: coupled hierarchical inductance model evaluation · DAC 2004

Methods — techniques the papers use, named apart from their topics

sparsification · 0.0hierarchical inductance model · 0.0
YearPublicationVenuePosition
2004 CHIME: coupled hierarchical inductance model evaluation
abstract
Modeling inductive effects accurately and efficiently is a critical necessity for design verification of high performance integrated systems. While several techniques have been suggested to address this problem, they are mostly based on sparsification schemes for the L or L-inverse matrix. In this paper, we introduce CHIME, a methodology for non-local inductance modeling and simulation. CHIME is based on a hierarchical model of inductance that accounts for all inductive couplings at a linear cost, without requiring any window size assumptions for sparsification. The efficacy of our approach stems from representing the mutual inductive couplings at various levels of hierarchy, rather than discarding some of them. A prototype implementation demonstrates orders of magnitude speedup over a full, flat model and significant accuracy improvements over a truncated model. Importantly, this hierarchical circuit simulation capability produces a solution that is as accurate as the hierarchically extracted circuits, thereby providing a "golden standard" against which simpler truncation based models can be validated.
Satrajit Gupta, Lawrence T. Pileggi
DAC1
2000 Hierarchical Interconnect Circuit Models
abstract
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable proportions. Interconnect extraction tools employ hierarchy to manage complexity, but this hierarchy is discarded via eliminating far away coupling terms when the equivalent ARC circuits are Formed. The increasing dominance of capacitance coupling along with the emergence of on chip inductance, however, makes the composite effect of far-away couplings increasingly evident. Even if newly enforced design rules and practices will ultimately obviate the need for modeling these couplings for design verification, some approximation of the "exact" solution is required to validate these rules. This paper proposes an efficient hierarchical equivalent circuit representation of interconnect parasitics that utilizes the efficient hierarchical long-distance modeling already existing within extractors. Results from a prototype simulator based on these hierarchical models demonstrate the simulation inaccuracy incurred when the faraway coupling terms are ignored. Such a form of interconnect modeling may provide the key to hierarchical modeling of electro-magnetic interactions between large components on future gigascale systems.
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi
ICCAD2