IEEE 1149.1-2013 provides compatible IEEE 1500 Wrapper Serial Port access for on-chip DFT and instrumentation access. This presentation shows how IEEE 1149.1-2013 integrates with IEEE 1500 WSPs and adds new capabilities such as wrapper segmentation for low power designs. Example architectures are presented with BSDL descriptions of IEEE 1500 WIRs and wrappers.

This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins. Unidirectional and bidirectional self-monitoring pins may contain sufficient series termination resistance and low enough voltage swings such that shorts between two pins become resistively isolated from the receivers and therefore are undetected during wiring interconnect tests. Potential solutions to mitigate the problem are offered.

A code-less processor that enables designers to achieve optimal in-system FPGA configuration as well as embed built-in self-test capabilities into boards and systems is presented. This system BIST architecture enables designers to lower system costs and design effort while satisfying test and field engineering requirements for simplified product test. The BIST processor described here provides a structured approach to solve these problems, using infrastructure IP designed for the board and system levels.

Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.

A two armed master-slave robot was modeled; simulations were run with a variety of compensation schemes using a payload with a compressive spring of 10,000 N/m and a preload force of 25 N against the payload. The slave arm was at first controlled by a simple linear force controller; this was inadequate with position step commands in that the force response oscillated greatly and resulted in crushing or dropping the payload. A low pass prefilter in the position command path corrected this, but so slowed the position response that significant tasks could not be carried out. These results illustrate the two way physical linkage between position output and force regulation dynamics. A second order, band pass cross filter sending position command as input into the forward loop of the force controller, enabled adequate position control dynamics and kept the payload force excursions to a minimum.