Nowadays, the transient error problem becomes one of the serious barriers to improve the high-performance application specific integrated circuit. This paper tackles the problem especially on the storage device (i.e., registers) since the transient error on registers can be quickly propagated to the entire system. To overcome the problem, Error Correcting Code (ECC) system has been recently studied in the high-level design stage. This paper improves this design by replacing some registers with radiation hardened registers to minimize the total cost of datapath. It proposes an integer linear programming-based method to simultaneously optimize ECC scheduling, register assignment, and register selection. Case studies on a benchmark circuit show the effectiveness of the approach.

Clock skew scheduling is a process of assigning intentional clock skews to registers for improving circuit performance and reliability. Due to the recent large effect of process variations, it becomes more and more difficult to reliably implement a large set of arbitrary clock latencies. Consequently, the optimization potential of clock skew scheduling should be highly limited. This paper points out that there is a chance to achieve further improvement of circuit performance by removing some register-writes while preserving functionality. This paper is the first work of the clock skew-aware high-level synthesis framework considering register write inhibition to minimize the clock period. A network flow-based heuristic algorithm to obtain the minimum clock period is presented and evaluated by experiments, which supports the effectiveness of the approach.

Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. A major downside of FF/latch-based design is the increase in resources (functional units and registers) due to the modification of the lifetimes of operations and data. Therefore, as a first step, this paper addresses the datapath design problem in which resource binding and register-type selection are simultaneously optimized for resource optimization. An efficient comprehensive framework is presented, which has flexibility to incorporate other design objectives. Experiments show that the proposed approach can generate resource-efficient FF/latch-based datapaths.

Moving into the era of nanoscale devices, reliable clock distribution becomes a challenging problem due to the growing impact of process variations. This paper deals with this difficulty, especially on implementing useful clock skew. One possible robust way is by using programmable delay elements (PDEs) since PDEs can be adjusted after fabrication. However, with this benefit, using PDEs takes large power cost. Based on the fact that the required clock skews are quite different, depending on registers, this paper proposes a register binding approach in high-level synthesis to minimize the number of PDEs for power reduction. A mixed integer linear programming is presented to formally draw up the problem. Experiments achieve 49.4% reduction of PDEs, compared to conventional design.

This paper proposes a novel high level synthesis for post-silicon skew adjustable datapaths. Our objective in high level synthesis is to maximize the "skew adjustability", i.e. the probability of the success of skew adjustment under delay variations. Skew adjustability is first shown to be reduced to the probability for a skew constraint graph (a weighted directed graph) to have no positive cycle. Since the computation of the skew adjustability is intractable, the original problem is transformed into "selective ordered coloring problem", which tries to minimize hazardous cycles instead of an exact skew adjustability. An ILP approach of the selective ordered coloring approach is then proposed. Experimental results show not only the effectiveness of our approach, but also how much improvement in the skew adjustability is achieved by equipping one or two extra registers to a datapath circuit.

This paper proposes a novel high-level synthesis (HLS) using double-edge-triggered flip-flops (DETFF) as memory elements. The duty-cycle is a key factor in the HLS. To utilize the duty-cycle radically, a variable-duty-cycle (VDC) mechanism is built into the HLS, which is captured by a new HLS task named VDC scheduling. As the first step for DETFF-based HLS, the clock-period minimization problem is formulated, and solved by a graph-based algorithm. The experimental results support the effectiveness of the algorithm.

In current VLSI complexity systems, clock skew scheduling is one of the key approaches to improve circuit performance and reliability. A delay insertion method has been discussed in logic-level to reduce the clock period. This paper extends this idea into high-level synthesis (HLS), and introduces a new HLS task, namely the minimum-path delay assignment. Since register binding plays an important role on the effect of the minimum-path delay assignment, this paper formulates the problem of simultaneously optimizing register binding and the minimum-path delay assignment. An MILP-based approach will be presented, and evaluated by experiment which shows the approach can reduce the clock period with an average of 14.1% compared to conventional clock skew-aware design.

Considering the timing uncertainty/variation of control signals and a clock signal to components, this paper proposes a novel resource sharing model which overcomes the risks of malfunctions caused by the timing problems. control timings, and proposes resource sharing conditions to FU assignment, which guarantee correct timings of control signals to multiplexers and registers under delay uncertainty/variation. This approach is combined with ``ordered clocking'' which is another mechanism to guarantee the correct timing, and the final resource sharing model is devised. There is a major drawback: the increase in latency. As the first step, the latency minimization problem under the proposed resource sharing model is formulated, and a simple List Scheduling-based algorithm is proposed as a solution algorithm. The proposed method is evaluated by experimental results for some benchmark circuits.

The setup and hold timing constraints are two types of timing constraints, which should be kept by each operation, and they may be violated by the timing variation of control signals. In this paper, we show that we can solve such potential timing violations in high-level synthesis without degrading speed performance, but by devising register assignment and clocking scheme. That is, we will combine Backward-Data-Direction (BDD) clocking, Forward-Data-Direction (FDD) clocking, and Structural Robustness against delay Variation (SRV)-based register assignment to solve potential timing violations. First, we formulate the problem as a minimum register assignment problem for datapaths which has a proper ordered clocking. After that, we propose an integer linear programming (ILP) formulation and show the experimental results for some benchmark circuits.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by contra-data-direction (CDD) clocking. After the formulation of this new register assignment problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by CDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.

Most of the stream mining techniques presented so far have primary paid attention to discovering association rules by direct comparison between time-series data sets. However, their utility is very limited for heterogeneous systems, where time series of various types (discrete, continuous, oscillatory, noisy, etc.) act dynamically in a strongly correlated manner. In this paper, we introduce a new nonlinear transformation, singular spectrum transformation (SST), to address the problem of knowledge discovery of causal relationships from a set of time series. SST is a transformation that transforms a time series into the probability density function that represents a chance to observe some particular change. For an automobile data set, we demonstrate that SST enables us to discover a hidden and useful dependency between variables.

The authors have developed a constraint-based method of describing features. Every feature is controlled by geometric constraints, which naturally specify the dimensioning information that reflects the designer's intent. An ATMS-based geometric reasoning system is proposed that efficiently evaluates the constraints in order to determine geometric attributes, and detects over-constrained situations in order to resolve conflicts among the constraints.>