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Michael James 0002

dblp:94/3826-2 · DBLP profile ↗
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5ranked-venue papers
1as first author
2since 2021 · last 2024
0009-0004-3808-8631ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 64% Hardware accelerators and domain-specific architectures · 17% Processor architecture and microarchitecture · 10%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
scientific computing systems
1.222024
Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System · SC 2024
Fast stencil-code computation on a wafer-scale processor · SC 2020
High-performance computing › scientific computing systems
molecular dynamics simulation
0.812024
Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System · SC 2024
Hardware accelerators and domain-specific architectures › many-core accelerator
wafer-scale engine
0.812024
Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System · SC 2024
High-performance computing › numerical linear algebra › linear solver
iterative linear solvers
0.412020
Fast stencil-code computation on a wafer-scale processor · SC 2020
High-performance computing
stencil computation
0.412020
Fast stencil-code computation on a wafer-scale processor · SC 2020
Processor architecture and microarchitecture › multicore design
waferscale processor
0.412020
Fast stencil-code computation on a wafer-scale processor · SC 2020
Machine learning › Deep learning architectures and training
normalization
0.412019
Online Normalization for Training Neural Networks · NeurIPS 2019
Memory systems
memory bandwidth
0.112020
Fast stencil-code computation on a wafer-scale processor · SC 2020
Machine learning › Deep learning architectures and training
recurrent neural network
0.112019
Online Normalization for Training Neural Networks · NeurIPS 2019

Methods — techniques the papers use, named apart from their topics

embedded atom method · 0.8dataflow algorithms · 0.8finite difference · 0.4BiCGStab · 0.4unbiased gradient estimation · 0.4automatic differentiation · 0.4
YearPublicationVenuePosition
2024 Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System
abstract
Molecular dynamics (MD) simulations have transformed our understanding of the nanoscale, driving breakthroughs in materials science, computational chemistry, and several other fields, including biophysics and drug design. Even on exascale supercomputers, however, runtimes are excessive for systems and timescales of scientific interest. Here, we demonstrate strong scaling of MD simulations on the Cerebras Wafer-Scale Engine. By dedicating a processor core for each simulated atom, we demonstrate a 457-fold improvement in timesteps per second versus the Frontier GPU-based Exascale platform, along with a large improvement in timesteps per unit energy. Reducing every year of runtime to less than a day unlocks currently inaccessible timescales of slow microstructure transformation processes that are critical for understanding material behavior and function.Our dataflow algorithm runs Embedded Atom Method (EAM) simulations at rates over 699k timesteps per second for problems with up to 800k atoms. This demonstrated performance is unprecedented for general-purpose processing cores.
Kylee Santos, Stan G. Moore, Tomas Oppelstrup, Amirali Sharifian, Ilya Sharapov, Aidan P. Thompson, Delyan Kalchev, Danny Perez, Robert Schreiber, Scott Pakin, Edgar A. León, James H. Laros III, Michael James 0002, Sivasankaran Rajamanickam
SC13
2021 ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing
abstract
Solving 3-D partial differential equations in a Finite Element model is computationally intensive and requires extremely high memory and communication bandwidth. This paper describes a novel way where the Finite Element mesh points of varying resolution are mapped on a large 2-D homogenous array of processors. Cerebras developed a novel supercomputer that is powered by a 21.5cm by 21.5cm Wafer-Scale Engine (WSE) with 850,000 programmable compute cores. With 2.6 trillion transistors in a 7nm process this is by far the largest chip in the world. It is structured as a regular array of 800 by 1060 identical processing elements, each with its own local fast SRAM memory and direct high bandwidth connection to its neighboring cores. For the 2021 ISPD competition we propose a challenge to optimize placement of computational physics problems to achieve the highest possible performance on the Cerebras supercomputer. The objectives are to maximize performance and accuracy by optimizing the mapping of the problem to cores in the system. This involves partitioning and placement algorithms.
Patrick Groeneveld, Michael James 0002, Vladimir Kibardin, Ilya Sharapov, Marvin Tom, Leo Wang
ISPD2
2020 ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator
abstract
This paper introduces a special case of the floorplanning problem for optimizing neural networks to run on a wafer-scale computing engine. From a compute perspective, neural networks can be represented by a deeply layered structure of compute kernels. During the training of a neural network, gradient descent is used to determine the weight factors. Each layer then uses a local weight tensor to transform "activations" and "gradients" that are shared among connected kernels according to the topology of the network. This process is computationally intensive and requires high memory and communication bandwidth. Cerebras has developed a novel computer system designed for this work that is powered by a 21.5cm by 21.5cm wafer-scale processor with 400,000 programmable compute cores. It is structured as a regular array of 633 by 633 processing elements, each with its own local high bandwidth SRAM memory and direct high bandwidth connection to its neighboring cores. In addition to supporting traditional execution models for neural network training and inference, this engine has a unique capability to compile and compute every layer of a complete neural network simultaneously. Mapping a neural network in this fashion onto Cerebras' Wafer-Scale Engine (WSE) is reminiscent of the traditional floorplanning problem in physical design. A kernel ends up as a rectangle of x by y compute elements. These are the flexible blocks that need to be placed to optimize performance. This paper describes an ISPD 2020 challenge to develop algorithms and heuristics that produce compiled neural networks that achieve the highest possible performance on the Cerebras WSE.
Michael James 0002, Marvin Tom, Patrick Groeneveld, Vladimir Kibardin
ISPD1
2020 Fast stencil-code computation on a wafer-scale processor
abstract
The performance of CPU-based and GPU-based systems is often low for PDE codes, where large, sparse, and often structured systems of linear equations must be solved. Iterative solvers are limited by data movement, both between caches and memory and between nodes. Here we describe the solution of such systems of equations on the Cerebras Systems CS-1, a wafer-scale processor that has the memory bandwidth and communication latency to perform well. We achieve 0.86 PFLOPS on a single wafer-scale system for the solution by BiCGStab of a linear system arising from a 7-point finite difference stencil on a 600 × 595 × 1536 mesh, achieving about one third of the machine's peak performance. We explain the system, its architecture and programming, and its performance on this problem and related problems. We discuss issues of memory capacity and floating point precision. We outline plans to extend this work towards full applications.
Kamil Rocki, Dirk Van Essendelft, Ilya Sharapov, Robert Schreiber, Michael Morrison, Vladimir Kibardin, Andrey Portnoy, Jean-Francois Dietiker, Madhava Syamlal, Michael James 0002
SC10
2019 Online Normalization for Training Neural Networks
abstract
Online Normalization is a new technique for normalizing the hidden activations of a neural network. Like Batch Normalization, it normalizes the sample dimension. While Online Normalization does not use batches, it is as accurate as Batch Normalization. We resolve a theoretical limitation of Batch Normalization by introducing an unbiased technique for computing the gradient of normalized activations. Online Normalization works with automatic differentiation by adding statistical normalization as a primitive. This technique can be used in cases not covered by some other normalizers, such as recurrent networks, fully connected networks, and networks with activation memory requirements prohibitive for batching. We show its applications to image classification, image segmentation, and language modeling. We present formal proofs and experimental results on ImageNet, CIFAR, and PTB datasets.
Vitaliy Chiley, Ilya Sharapov, Atli Kosson, Urs Köster, Ryan Reece, Sofia Samaniego de la Fuente, Vishal Subbiah, Michael James 0002
NeurIPS8