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Dan P. Baumberger

dblp:94/3900 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Operating systems · 70% Concurrent programming · 30%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Embedded and real-time systems · 41% Parallel and multicore computing · 41% Processor architecture and microarchitecture · 18%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Operating systems › resource management › process management
CPU scheduling
0.222009
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin · PPoPP 2009
Efficient operating system scheduling for performance-asymmetric multi-core architectures · SC 2007
Concurrent programming
fair scheduling
0.112009
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin · PPoPP 2009
Embedded and real-time systems › real-time scheduling
multiprocessor scheduling
0.112009
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin · PPoPP 2009
Parallel and multicore computing › task scheduling › process scheduling
proportional share scheduling
0.112009
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin · PPoPP 2009
Operating systems › resource management › process management › CPU scheduling
NUMA-aware scheduling
0.012007
Efficient operating system scheduling for performance-asymmetric multi-core architectures · SC 2007
Processor architecture and microarchitecture › multicore design › heterogeneous multicore
asymmetric multicore
0.012007
Efficient operating system scheduling for performance-asymmetric multi-core architectures · SC 2007
Processor architecture and microarchitecture
multicore design
0.012007
Efficient operating system scheduling for performance-asymmetric multi-core architectures · SC 2007

Methods — techniques the papers use, named apart from their topics

proportional fairness analysis · 0.2distributed thread queues · 0.2load balancing · 0.1CPU clock modulation · 0.1
YearPublicationVenuePosition
2009 Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin
abstract
Fairness is an essential requirement of any operating system scheduler. Unfortunately, existing fair scheduling algorithms are either inaccurate or inefficient and non-scalable for multiprocessors. This problem is becoming increasingly severe as the hardware industry continues to produce larger scale multi-core processors. This paper presents Distributed Weighted Round-Robin (DWRR), a new scheduling algorithm that solves this problem. With distributed thread queues and small additional overhead to the underlying scheduler, DWRR achieves high efficiency and scalability. Besides conventional priorities, DWRR enables users to specify weights to threads and achieve accurate proportional CPU sharing with constant error bounds. DWRR operates in concert with existing scheduler policies targeting other system attributes, such as latency and throughput. As a result, it provides a practical solution for various production OSes. To demonstrate the versatility of DWRR,we have implemented it in Linux kernels 2.6.22.15 and 2.6.24, which represent two vastly different scheduler designs. Our evaluation shows that DWRR achieves accurate proportional fairness and high performance for a diverse set of workloads.
Tong Li 0003, Dan P. Baumberger, Scott Hahn
PPoPP2
2007 A Hybrid Real-Time Scheduling Approach for Large-Scale Multicore Platforms
abstract
We propose a hybrid approach for scheduling real-time tasks on large-scale multicore platforms with hierarchical shared caches. In this approach, a multicore platform is partitioned into clusters. Tasks are statically assigned to these clusters, and scheduled within each cluster using the preemptive global EDF scheduling algorithm. We show that this hybrid of partitioning and global scheduling performs better on large-scale platforms than either approach alone. We also determine the appropriate cluster size to achieve the best performance possible, given the characteristics of the task set to be supported.
John M. Calandrino, James H. Anderson, Dan P. Baumberger
ECRTS3
2007 Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms
abstract
This paper discusses an approach for supporting soft real-time periodic tasks in Linux on performance asymmetric multicore platforms (AMPs). Such architectures consist of a large number of processing units on one or several chips, where each processing unit is capable of executing the same instruction set at a different performance level. We discuss deficiencies of Linux in supporting periodic real-time tasks, particularly when cores are asymmetric, and how such deficiencies were overcome. We also investigate how to provide good performance for non-real-time tasks in the presence of a real-time workload. We show that this can be done by using deferrable servers to explicitly reserve a share of each core for non-real-time tasks. This allows non-real-time tasks to have priority over real-time tasks when doing so will not cause timing requirements to be violated, thus improving non-real-time response times. Experiments show that even small deferrable servers can have a dramatic impact on non-real-time task performance
John M. Calandrino, Dan P. Baumberger, Tong Li 0003, Scott Hahn, James H. Anderson
IEEE Real-Time and Embedded Technology and Applications Symposium2
2007 Efficient operating system scheduling for performance-asymmetric multi-core architectures
abstract
Recent research advocates asymmetric multi-core architectures, where cores in the same processor can have different performance. These architectures support single-threaded performance and multithreaded throughput at lower costs (e.g., die size and power). However, they also pose unique challenges to operating systems, which traditionally assume homogeneous hardware. This paper presents AMPS, an operating system scheduler that efficiently supports both SMP-and NUMA-style performance-asymmetric architectures. AMPS contains three components: asymmetry-aware load balancing, faster-core-first scheduling, and NUMA-aware migration. We have implemented AMPS in Linux kernel 2.6.16 and used CPU clock modulation to emulate performance asymmetry on an SMP and NUMA system. For various workloads, we show that AMPS achieves a median speedup of 1.16 with a maximum of 1.44 over stock Linux on the SMP, and a median of 1.07 with a maximum of 2.61 on the NUMA system. Our results also show that AMPS improves fairness and repeatability of application performance measurements.
Tong Li 0003, Dan P. Baumberger, David A. Koufaty, Scott Hahn
SC2