Routing-dominated multi-path architectures play a critical role in enhancing data throughput and resource efficiency in computing, communication, and RF systems. Hence, ensuring matched point-to-point signal arrival is critical to minimizing distortion, latency, and data corruption while managing increased routing density and interconnect complexity. In this paper, delay mismatch in routing-dominated systems is investigated while assuming negligible mismatch within circuit blocks. A variancebased framework is proposed to quantify and optimize the delay mismatch components across multiple levels of abstraction: the system, block, and layout. To validate this model, systematic routing optimization techniques are applied to an impulse-radio ultra-wideband (IR-UWB) edge-combiner transmitter front end (TFE) operating at $6.5-8.0 \mathrm{GHz}$ center frequency. The TFE requires precise pulse widths in the picosecond range, making it highly susceptible to interconnect-induced delay variability. After optimization, the total variance of propagation delay was decreased by 94.37% based on post-layout simulations.

This paper presents a passive 5.8GHz RF Energy Harvester (RFEH) implemented in 65nm CMOS technology that allows batteryless operation and reduction in overall size of WSN and IoT sensor nodes, which are limiting more widespread implementation. The RFEH consists of an on-chip matching network and optimized rectifier that are co-designed for maximum efficiency and sensitivity in the RFEH in gathering the required energy for the load circuit. The passive 5.8GHz RFEH prototype demonstrated a sensitivity of around -13dBm in gathering enough energy to produce 0.5V on a 10uF capacitive load, allowing the harvested energy to be reasonably combined with energy from other sources. When used as the only energy source, the ability to gather and provide a continuous supply of 8uW (10uA at 0.8V) is demonstrated, which is enough to power low-power RF circuits such as OOK and FSK receivers without the need of any battery, allowing batteryless operation.

A 450kHz 30kbps all-digital BPSK demodulator is implemented in 65nm CMOS. Correlation and carrier recovery algorithms are designed to be PVT-aware through digital correction. The target BER of 10-6 is achieved through 16 symbol per bit redundancy with 8× oversampling. An 8-bit tunable oscillator is utilized with corresponding frequency and phase locking techniques to maintain packet synchronization. The demodulator is designed to operate on 3.6MHz in 500mV supply with enough margin to compensate for variations due to 10% supply voltage ripple, and 0°C to 100° C operating temperatures.

Digital circuits are more resilient to PVT variations, has smaller area and lower power consumption than analog circuits. In this paper, two digital techniques, wait state and time slot, were used to solve the timing failures in the operation of the digital processing block of a power line sensor node. In this sensor node design, timing failures occur because of two reasons: 1) the power-on reset (POR) circuits are switching early and 2) the storage capacitor of the energy harvesting block cannot fully support the required energy during transmit operations. Using wait states, timing failures were prevented by providing timing margin between the POR switching and the activation of the digital blocks. The counters to implement the wait states only contributed 2% additional area and 5% addition al power consumption to the digital processor. The time slot technique, on the other hand, prevented timing failures by providing a schedule for the transmit operation to execute only at a time when Pin is higher than Ptransmit. Using this technique, the size of the storage capacitor of the energy harvesting block was reduced 50 times compared when the technique is not used. The power line sensor node was successfully fabricated in 65nm CMOS process with an area of 4.84mm2and was designed to work at a noisy voltage supply of 500mV with a voltage ripple of 15mV peak to peak and a wide temperature range of 0°C to 120°C.

Unlike static CMOS circuits, the standby energy in sense amplifier-based pass transistor logic (SAPTL) circuits can be decoupled from its performance, allowing separate optimization strategies for leakage and speed. In this paper, a 64-byte parallel cyclic-redundancy check (CRC) generator is designed and implemented using asynchronous 90nm SAPTL circuits, with a simulated minimum energy point that is 25% lower than the equivalent complementary static CMOS implementation. The low leakage operation results in (a) an 7.9X reduction in measured energy when VDDis reduced from 1V to 0.3V at α = 0.1 and (b) a 10% reduction in measured delay with a stack forward body bias of 0.4V, with no corresponding increase in energy.

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.

To achieve an increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs) are used. However, there is a need to analyze the suitability of floating-point architectures for high-speed or low power applications. In this research, different system-level architectures and operational algorithms of FPUs were implemented using 0.25mum CMOS standard cells. Fair comparison of design metrics in terms of speed, area and power consumption were made and analyzed for each design. Simulation results show that architectures with an independent pipeline for division perform better in terms of speed while combined pipelines consume the least power. Also, architectures with a combined pipeline for addition and multiplication and an independent pipeline for division occupy the smallest layout area and, in general, show the best performance in all three metrics