Deep Reinforcement Learning (DRL) algorithms have achieved great success in solving many challenging tasks while their black-box nature hinders interpretability and real-world applicability, making it difficult for human experts to interpret and understand DRL policies. Existing works on interpretable reinforcement learning have shown promise in extracting decision tree (DT) based policies from DRL policies with most focus on the single-agent settings while prior attempts to introduce DT policies in multi-agent scenarios mainly focus on heuristic designs which do not provide any quantitative guarantees on the expected return. In this paper, we establish an upper bound on the return gap between the oracle expert policy and an optimal decision tree policy. This enables us to recast the DT extraction problem into a novel non-euclidean clustering problem over the local observation and action values space of each agent, with action values as cluster labels and the upper bound on the return gap as clustering loss. Both the algorithm and the upper bound are extended to multi-agent decentralized DT extractions by an iteratively-grow-DT procedure guided by an action-value function conditioned on the current DTs of other agents. Further, we propose the Return-Gap-Minimization Decision Tree (RGMDT) algorithm, which is a surprisingly simple design and is integrated with reinforcement learning through the utilization of a novel Regularized Information Maximization loss. Evaluations on tasks like D4RL show that RGMDT significantly outperforms heuristic DT-based baselines and can achieve nearly optimal returns under given DT complexity constraints (e.g., maximum number of DT nodes).

Cybersecurity at the edge requires fast computing in energy-constrained environments. Decision trees can provide an explainable solution for network intrusion detection with high detection accuracy at the packet level. However, their hardware implementation needs to support efficient real-time operation. In this paper, we propose a spatially distributed decision tree for network intrusion detection, using memristor-based chiplet leaves. Each chiplet processes an input by comparing it to a predefined boundary stored in the memristor cell and provides a binary output to select one of the interconnected leaves on the lower level, with an estimated power consumption in a 130nm node design of 389$\mu$W. The delay is 2.5$\mu$s for one inference decision. This chiplet approach is reconfigurable and in line with the natural architecture of decision trees. It also supports the prototyping with known good dies, overcoming the non-idealities challenge prevalent in memristor technologies. Our memristor-based decision trees show high intrusion detection accuracy of 82%, 84%, and 73% on the benchmark UNSW, CIC-IDS, and ACI-IoT datasets respectively, considering 6-bit device precision in one memristor vs. three memristor per boundary configurations. This distributed approach opens the way to utilizing memristor technology despite device defects for applications in need of local real-time computing.

The movement of large quantities of data during the training of a deep neural network presents immense challenges for machine learning workloads, especially those based on future functional memories deployed to store network models. As the size of network models begins to vastly outstrip traditional silicon computing resources, functional memories based on flash, resistive switches, magnetic tunnel junctions, and other technologies can store these new ultra-large models. However, new approaches are then needed to minimize hardware overhead, especially on the movement and calculation of gradient information that cannot be efficiently contained in these new memory resources. To do this, we introduce streaming batch principal component analysis (SBPCA) as an update algorithm. Streaming batch principal component analysis uses stochastic power iterations to generate a stochastic rank- k approximation of the network gradient. We demonstrate that the low-rank updates produced by streaming batch principal component analysis can effectively train convolutional neural networks on a variety of common datasets, with performance comparable to standard mini-batch gradient descent. Our approximation is made in an expanded vector form that can efficiently be applied to the rows and columns of crossbars for array-level updates. These results promise improvements in the design of application-specific integrated circuits based around large vector-matrix multiplier memories.

High-performance radio frequency (RF) switches play a critical role in allowing radio transceivers to provide access to shared resources such as antennas. They are important, especially in reconfigurable radios, where the connections within and between the different blocks (e.g., filters, amplifiers, and mixers) can be changed to customize and compose RF functions for distinct frequency bands. To realize this potential, new concepts for RF switch devices that can be integrated with standard transistor process, while providing better transmission performance, lower power consumption, smaller area, and lower actuation voltage than current RF switch technologies [e.g., field-effect transistors (FETs) and microelectromechanical systems (MEMSs)] are needed. Recently, RF switches based on emerging memory technologies, such as conductive-bridge RAM (CBRAM), resistive RAM (ReRAM), and phase-change memory (PCM), have been proposed. These nanoscale switches present major advantages, for example, high cutoff frequency, nonvolatility, fast and low-energy switching, small footprint, and compatibility with back-end-of-line (BEOL) of the standard CMOS process, thus placing them as possible contenders for high-performance RF switches. This article surveys high-performance RF switches based on resistive memories, comparing them with mature RF switching technologies like RF MEMS, p-i-n diodes, and FETs. We discuss the physical mechanisms, device structure, performance characteristics, and applications of these novel RF switches. Furthermore, we examine the prospects and future research directions of these technologies that could lead to their adoption at the industrial level.

Faster and more energy efficient hardware accelerators are critical for machine learning on very large datasets. The energy cost of performing vector-matrix multiplication and repeatedly moving neural network models in and out of memory motivates a search for alternative hardware and algorithms. We propose to use streaming batch principal component analysis (SBPCA) to compress batch data during training by using a rank-k approximation of the total batch update. This approach yields comparable training performance to minibatch gradient descent (MBGD) at the same batch size while reducing overall memory and compute requirements.

This is a brief review of our recent work on memristor-based spiking neuromorphic networks. We first describe the recent experimental demonstration of several most biology-plausible spike-time-dependent plasticity (STDP) windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. We then discuss recent theoretical work in which an analytical, data-verified STDP model was used to simulate operation of a spiking classifier of spatial-temporal patterns, and the capacity-to-fidelity tradeoff and noise immunity o f spiking spatial-temporal associative memories with local and global recording was evaluated.

Science, technology and engineering are constantly changing in profound ways, so STEM teachers have to keep up with providing not only the textbook basics, but also updated examples from current technologies, while using novel teaching techniques based on scientific inquiry. Professional development activities are powerful tools to increase teacher learning, and indirectly drive improved classroom practices and student learning. The literature regarding teacher professional development has reached considerable consensus regarding the features of the PD activities that lead to successful programs. However, the literature shows an insufficient analysis of the teacher motivation to attend professional development activities. In order to attract teachers and maintain their sustained involvement in professional activities, these activities need to be designed keeping in mind the teachers' background and motivation. This paper examines the factors that contribute to the science and technology high school teachers in Chile participating in professional development activities. These findings will fill in a gap in the literature and could inform the design of professional development programs in Chile and abroad.

We present preliminary results towards realization of three dimensional material implication logic with monolithically stacked TiO2-based memristive devices. As a first step towards our goal we have fabricated and successfully demonstrated resistive switching for top and bottom layer memristors of the bilayer device stack. The 3D aspect of the circuits, which is a main novelty of our work, enables much higher performance of implication logic as compared to planar case. More generally, our research could be applied to digital memories and hybrid programmable logic which would benefit from 3D monolithical integration.