SRAM cell design is driven by the need to satisfy several stability and performance criteria for all cells in the array in an energy-efficient manner. Significant randomness of FET threshold voltages makes achieving this difficult and limits both the minimum cell size and minimum array supply voltage. Post-silicon adaptivity in the form of an adaptive-voltage scheme in a partitioned SRAM array can be used to reduce impact of variability despite lack of any spatial correlation in realizations. This paper develops a novel optimization flow for yield-aware cell sizing and voltage selection under variability given the availability of post-silicon voltage tuning. We formulate a two-stage stochastic optimization problem in which the first-stage decision is to select cell size and possible voltage levels, and the second-stage decision is to assign each partition to an optimal voltage after manufacturing. We develop closed-form statistical models of array margin behavior and yield as a function of Vdd, cell size, and array size. We solve the problem using dynamic programming that minimizes power while meeting yield constraints on read, write, and static noise margins. The proposed flow allows designs that are on average 8% and up to 17% more power-efficient than the designs in which voltages are selected uniformly. The results also indicate that at high-yield levels power savings can be up to 32% in the active mode and 71% in the standby mode.

An intrinsic notion of quality floors present in typical digital signal processing circuits can be used to strategically accept some runtime errors in exchange for a reduction in energy consumption. Conventional very large scale integration design strategies do not exploit this degree of error tolerance and aim to guarantee timing correctness, thereby sacrificing energy efficiency. In this paper, we propose techniques for timing error acceptance to improve the quality-energy tradeoff in image and video processing systems under scaledVDD. The basic philosophy is to prevent signal quality from severe degradation, on average, by using data statistics. The introduced innovations include techniques for carefully controlling possible errors and exploiting the specifics of error patterns for low-cost postprocessing to minimize quality degradation. We demonstrate the effectiveness of the proposed techniques on a 2-D inverse discrete cosine transform (IDCT) and a 2-D DCT design. The designs were synthesized using a 45-nm standard cell library, with energy and delay evaluated using NanoSim and VCS. Experiments show that direct applications of controlled error-acceptance techniques allow up to 59% and 71% energy savings by permitting fewer than 1-dB peak signal-to-noise ratio (PSNR) decrease for the 2-D IDCT and DCT designs, respectively. The resulting PSNR remains above 30dB, which is a commonly accepted value for lossy image and video compression. Achieving such energy savings by directVDDscaling without the proposed transformations results in a 12-dB PSNR loss. The area overhead for the needed control logic is about 4.8% of the original design. To further minimize quality degradation caused by accepted errors in the IDCT, we introduce postfiltering on the output image. The significant improvement of the perceived image quality allows further voltage scaling leading to overall energy savings of 70% for the 2-D IDCT, while costing an additional 1.1% in area.

Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. We identify a fundamental trade-off between error frequency and error magnitude in a timing-starved adder. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits.

In embedded digital signal processing (DSP) systems, quality is set by a signal-to-noise ratio (SNR) floor. Conventional digital design strategies guarantee timing correctness of all operations, which leaves large quality margins in practical systems and sacrifices energy efficiency. This paper presents techniques to significantly improve energy efficiency by shaping the quality-energy tradeoff achievable via VDDscaling. In an unoptimized design, such scaling leads to rapid loss of quality due to the onset of timing errors. We introduce techniques that modify the behavior of the early and worst timing error offenders to allow for larger VDDreduction. We demonstrate the effectiveness of the proposed techniques on a 2D-IDCT design. The design was synthesized using a 45nm standard cell library. The experiments show that up to 45% energy savings can be achieved at a cost of 10dB peak signal-to-noise ratio (PSNR). The resulting PSNR remains above 30dB, which is a commonly accepted value for lossy image and video compression. Achieving such energy savings by direct VDDscaling without the proposed transformations results in a 35dB PSNR loss. The overhead for the needed control logic is less than 3% of the original design.

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These constraints determine both the minimum cell size and supply voltage. RCM is set by the maximum read access time over the array. The randomness of transistor threshold voltages, and thus read times, makes maximum read time follow extreme order statistics, specifically, the Gumbel distribution which is characterized by long tails. Thus, the margin specification needs to be met at the high sigma corners in order to reach acceptable yield, resulting in oversizing and increased VDD. In this work, we demonstrate that a reduced-area bitcell design is achievable by reducing the impact of intra-array randomness through a new architecture that employs an adaptive voltage scheme in a partitioned SRAM array. The key idea is to be able to shift empirical distributions (realizations) of read time in a set of rows that form a single partition to meet the target. Because the partition is smaller than the whole array, the tail of the Gumbel distribution is significantly reduced. The adaptive voltage tuning policy is driven by the worst partition access time. For the blocks whose delay violates access time constraints, a higher voltage is selected out of the available set to gain yield, otherwise voltage is reduced for power saving. This permits smaller cell area and lower V DD at identical yield. The cost of adaptivity is in generation and routing of a small number (in our experiments, four) voltage levels and the area of one-per-partition set of PMOS switches. We demonstrate that through the voltage tuning architecture we propose, it is possible to obtain mean power consumption reduction on average by 21% iso-area. Alternatively, bitcell area can be reduced on average by 7% iso-power compared to the existing design strategy.

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4times-9times LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000times faster than the MILP method within an acceptable loss of accuracy.

As technology scales, negative bias temperature instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, the authors first investigate the impact of NBTI on PMOS devices and propose a novel temporal performance degradation model for digital circuits considering the temperature difference between active and standby mode. For the first time, the impact of input vector control (to minimize standby leakage) on the NBTI is investigated. Minimum leakage vectors, which lead to minimum circuit performance degradation and remains maximum leakage reduction rate, are selected and used during the standby mode. Furthermore, the potential to save the circuit performance degradation by internal node control techniques during circuit standby mode is discussed. Our simulation results show that: 1) the active and standby time ratio and the standby mode temperature have considerable impact on the circuit performance degradation; 2) the NBTI-aware IVC technique leads to an average 3% savings of the total circuit degradation; while the potential of internal node control may lead to 10% savings of the total circuit degradation

Power gating is an effective method to reduce leakage power during the circuit sleep mode; however, it introduces the ground bounce problem and has considerable energy consumption during the mode transitions. To mitigate the ground bounce, we propose a novel power gating scheme that reduces the magnitude of the peak current and voltage glitches as well as the time to stabilize power and ground during mode transitions. To further decrease the wakeup time while keep the energy efficiency, we introduce two improved circuit schemes with two intermediate states, based on our proposed power gating scheme. The scheme provides an average peak voltage reduction of 67.0%, and the wakeup time reduction is up to 62.3%. If the circuits use the intermediate schemes, wakeup time can be further reduced by a maximum of 95.7%. Beside these reductions, our proposed circuit scheme also has the advantage of small size and flexible controllability.