It is a complex task to model event-handling in class diagrams. In this paper, we suggest a new approach, in which the Object Constraint Language is extended by the ability to register event handlers for an event source. This approach helps to create real platform independent models for the Model Driven Architecture technology. The benefit of our new approach is that event-handling can be modeled in class diagrams concisely and uniformly.

We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don't-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably non-redundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.

The functional decomposition is known as a method to design digital circuits. The authors want to demonstrate and prove a way to design fully testable combinatorial circuits by this method. Furthermore, they show the opportunity of calculating the test pattern instantly during the synthesis. This pattern generation uses the same data and function terms as the generation of the circuit structure and so it causes only small additional expense.>