In recent years, the growing demand for connected technologies has lead to an exponential surge in the number of IoT devices worldwide. This has resulted in the IoT ecosystems been relentlessly targeted by cyber criminals with the sole aim of compromising the IoT devices. Such compromised devices exhibit abnormal behavior that are manifested in the corresponding network traffic patterns. Anomalous network traffic behavior can be detected with the help of IoT device fingerprinting. Device fingerprinting involves analysis of the network traffic patterns of the IoT devices to create a unique digital blueprint of each of the devices. Such blueprints help to distinguish between normal and abnormal device behaviors, thereby providing indications of possible device compromise and also to detect the presence of a new device. In this paper, we propose an IoT device fingerprinting strategy that uses a sliding window based approach to analyze the characteristics of the network traffic generated by the IoT devices. Our fingerprinting strategy performs packet-level network traffic analysis. However, instead of considering the individual network packets, the proposed sliding window based method aggregates a fixed number of packets to create the device fingerprints. Moreover, the method ensures overlap between successive windows while aggregating the packets to retain the temporal relationships among the different packets of a single IoT device. We name our strategy as SINTTRA, Sliding wINdow based Temporally aware neTwork tRaffic Analyzer. SINTTRA uses supervised machine learning for categorizing the different IoT devices. We have evaluated the efficacy of SINTTRA on network traffic traces collected from our own IoT testbed setup as well as the open-source UNSW IoT dataset. We have also compared the performance of SINTTRA with the flow-based network traffic analysis for device fingerprinting. For both datasets, SINTTRA performs better than the flow-based approach by a margin of 2% to 10% in terms of accuracy, precision, recall and F1-score.

Emerging byte-addressable, non-volatile memory technologies offer performance within an order of magnitude of DRAM, prompting their inclusion in the processor memory subsystem. However, such load/store accessible Persistent Memory (PM) has implications on system design, both hardware and software. In this paper, we explore system software support to enable low-overhead PM access by new and legacy applications. To this end, we implement PMFS, a light-weight POSIX file system that exploits PM's byte-addressability to avoid overheads of block-oriented storage and enable direct PM access by applications (with memory-mapped I/O). PMFS exploits the processor's paging and memory ordering features for optimizations such as fine-grained logging (for consistency) and transparent large page support (for faster memory-mapped I/O). To provide strong consistency guarantees, PMFS requires only a simple hardware primitive that provides software enforceable guarantees of durability and ordering of stores to PM. Finally, PMFS uses the processor's existing features to protect PM from stray writes, thereby improving reliability.

Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding architects to consider heterogeneous chips and platforms for the next decade and beyond. Exploring heterogeneous architectures is challenging since it involves re-evaluating architecture options, OS implications and application development. In this paper, we describe these research challenges and then introduce a heterogeneous prototype platform called QuickIA that enables rapid exploration of heterogeneous architectures employing multiple generations of Intel processors for evaluating the implications of asymmetry and FPGAs to experiment with specialized processors or accelerators. We also show example case studies using the QuickIA research prototype to highlight its value in conducting heterogeneous architecture, OS and applications research.

Heterogeneous architectures that integrate a mix of big and small cores are very attractive because they can achieve high single-threaded performance while enabling high performance thread-level parallelism with lower energy costs. Despite their benefits, they pose significant challenges to the operating system software. Thread scheduling is one of the most critical challenges.

A heterogeneous processor consists of cores that are asymmetric in performance and functionality. Such a design provides a cost-effective solution for processor manufacturers to continuously improve both single-thread performance and multi-thread throughput. This design, however, faces significant challenges in the operating system, which traditionally assumes only homogeneous hardware. This paper presents a comprehensive study of OS support for heterogeneous architectures in which cores have asymmetric performance and overlapping, but non-identical instruction sets. Our algorithms allow applications to transparently execute and fairly share different types of cores. We have implemented these algorithms in the Linux 2.6.24 kernel and evaluated them on an actual heterogeneous platform. Evaluation results demonstrate that our designs efficiently manage heterogeneous hardware and enable significant performance improvements for a range of applications.

Simulation methods have become an integral part of almost all aspects of networking research and particularly in the area of wireless networks. Any new protocol or methodology that is proposed for wireless networks almost always will be demonstrated using simulations. However, there is little evidence that existing models of physical layer signal propagation and signal strength calculations produce realistic or meaningful results. Indeed, there have been a number of empirical studies that have shown little predictability in measured signal strength and packet receipt probability for deployed networks. Common assumptions used in simulation models about the behavior of the wireless signal have been shown to often be invalid. These prior works motivated us to design a stochastic model for wireless signal propagation in our GTNetS simulator. Our model is based on a detailed empirical measurement study and uses random variations to produce more realistic behavior for wireless packet transmissions and reception modeling.

Network Simulation tools have played very significant role in wireless network research in the past decade. Compared to wired networks, there are a lot more parameters that effect the behavior of wireless networks. For reasons of simplicity and computational complexity, some details are abstracted out when implementing protocol models in network simulators. IEEE 802.11 has been the dominant protocol for the MAC and PHY layers of most wireless networks in practice. Subtle implementation variations in the 802.11 protocol result in largely divergent results when higher level protocols are simulated on top of the 802.11MAC. In this paperwe concentrate on these implementation details and show how these affect the behavior of the 802.11 MAC model in various simulators. We also identify the abstractions that result in the diverging behavior of the 802.11 MAC protocol model and try to compare those with reference to the IEEE specification.

We present a sensor network simulation environment that allows users to evaluate the effects of different architectural choices and strategies on the lifetime and performance of a sensor network. Our tool can also be used to evaluate new approaches (routing protocols, cooperation algorithms), and compare them with the ones already in place. This simulator is an extension of the Georgia Tech Network Simulator (GTNetS) and leverages its design choices for maximum performance. It incorporates models for the different functional units composing a sensor node and characterizes the energy consumption of each. It also has a model for a network base station and its interactions with the rest of the network. We report our results from a set of tests that demonstrate some of the capabilities of our simulator. In particular, we were able to simulate sensor networks of several hundred thousand nodes while using less than 2 GB of memory, which exceeds the capabilities of existing simulators by an order of magnitude. The simulator is also used to study the performance of an algorithm that assigns globally unique IDs to nodes in a sensor network.