As microprocessor designs integrate more cores, scalability of cache coherence protocols becomes a challenging problem. Most directory-based protocols avoid races by using blocking tag directories that can impact the performance of parallel applications. In this article, we first quantitatively demonstrate that state-of-the-art blocking protocols significantly constrain throughput at large core counts for several parallel applications. Nonblocking protocols address this throughput concern at the expense of scalability in the interconnection network or in the required resource overheads. To address this concern, we enhance nonblocking directory protocols by migrating the point of service of responses. Our approach uses in-flight chains of cores making parallel memory requests to incorporate scalability while maintaining high-throughput. The proposed cache coherence protocol called chained cache coherence , can outperform blocking protocols by up to 20% on scientific and 12% on commercial applications. It also has low resource overheads and simple address ordering requirements making it both a high-performance and scalable protocol. Furthermore, in-flight chains provide a scalable solution to building hierarchical and nonblocking tag directories as well as optimize communication latencies.

This paper discusses modeling requirements of network traffic over next-generation internets and intranets. This traffic will include not only traditional data, but continuous media and multimedia services like telephony, digital television, and interactive TV. We propose a model for interactive TV and discuss its relationship to traditional data and media traffic models. We also present simulation results using this model to compare network bandwidth allocation strategies based on the measured characteristic of on actual interactive TV application used in medical training.

Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated circuits, or developing designs which use an array of processors. Pixel-Planes 1–5 and PixelFlow‡ are examples of architectures which use an array of pixel processors for rasterization. Early generations of Pixel-Planes attempted to make these arrays as large as the display providing one processor for each display pixel. Later generations improved performance by grouping processors into multiple smaller arrays, subdividing the screen into sections of a corresponding size and having the arrays independently process the screen subdivisions. This paper describes simulations which were performed to determine the optimum size subdivision for a graphics computer which uses Pixel-Planes type parallelism, i.e. static two dimensional screen subdivision parallel polygon rasterization. We then develop a mathematical approach to determining the optimal subdivision size and show that it agrees well with the experimental data. For special purpose architectures we show that the optimal size depends not only on the polygon size but also on the silicon area consumed by the rasterizer overhead. The mathematical approach can be directly applied to special purpose architectures, and we show how it can be modified for use in analyzing algorithms developed for general purpose architectures such as the Intel Touchstone or Paragon, or the Thinking Machines CM-5.

This paper examines nonloop parallelism at both fine and coarse levels of granularity in ordinary Fortran programs. Dynamic self-scheduling algorithms are developed for acyclic task graphs containing both data- and control-dependences, along with the compiler optimizations necessary to make these practical. It is shown that practical algorithms based on atomicfetch-and-φ operations to a single shared variable, similar in spirit to dynamic loop dispatching algorithms, are possible for acyclic task graphs. Further, they generalize easily todoacrossloops. A key requirement is the use of compiler algorithms to optimize the task graphs. We show that although exact redundant dependence removal is theoretically NP-hard, the practical complexity on actual codes is small. Performance-related measurements are given to characterize the algorithms on a set of standard benchmark codes.

A special-purpose hardware scheme uniquely tailored to barrier synchronization is presented. It allows barrier synchronization to be performed within a single instruction cycle for moderately sized systems, and is scalable with logarithmic increase in synchronization time. It supports a large number of concurrent barriers, and can also be used to support a number of different barrier synchronization schemes. The hardware is relatively simple and inexpensive. Simulation results have shown that, under reasonable assumptions, it can decrease typical parallel-loop execution time significantly, especially for fine-grained and statically scheduled loops.>