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Shigeo Kamiya

dblp:96/4441 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Integrated circuit design · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › database accelerator
database machine		 0.011985
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware · ISCA 1985
Integrated circuit design › digital circuit design › VLSI architecture
sorting hardware		 0.011985
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware · ISCA 1985

Methods — techniques the papers use, named apart from their topics

two-way merge sort · 0.0hardware pipeline · 0.0
YearPublicationVenuePosition
1985 A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware
abstract
A relational database machine Delta [2] has been developed at the Institute for New Generation Computer Technology (IOOT).The main component of Delta is an RDBE (relational database engine)[3] which performs relational database operations, such as projection and join.The RDBE consists of a sorting process hardware module called the sorter, a merging process hardware module called the merger, other special hardware modules called the IN module, a data input adapter, a data output adapter, and a CPU controlling these hardware modules.A special sorting cell was developed and implemented on LSI.The sorting process is based on a two-way merge-sort algorithm [l].~ne merging process is based on a hardware pipeline algorithm.In this paper, we describe the design considerations of the RDBE and these algorithms.Then, we describe the detailed design, implementation, and a performance evaluation of the RDBE.
Shigeo Kamiya, Kazuhide Iwata, Hiroshi Sakai, Susumu Matsuda, Shigeki Shibayama, Kunio Murakami
 ISCA1