This paper addresses three topics: First, a new three-dimensional CMOS-SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are l00nm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration like for example the reduced length of interconnections. A 16×l6 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given here in terms of energy consumption, delay and area

The paper presents a general theory for developing new Svoboda-Tung (or simply NST) division algorithms not suffering the drawbacks of the "classical" Svoboda-Tung (or simply ST) method. NST avoids the drawbacks of ST by proper recoding of the two most significant digits of the residual before selecting the most significant digit of this recoded residual as the quotient digit. NST relies on the divisor being in the range [1, 1+/spl delta/), where /spl delta/ is a positive fraction depending upon: 1) the radix, 2) the signed digit set used to represent the residual, and 3) the recoding conditions of the two most significant digits of the residual. If the operands belong to the IEEE Std range [1, 2), they have to be conveniently prescaled. In that case, NST produces the correct quotient but the final residual is scaled by the same factor as the operands, therefore, NST is not useful in applications where the unsealed residual is necessary. An analysis of NST shows that previously published algorithms can be derived from the general theory proposed in the paper. Moreover, NST reveals a spectrum of new possibilities for the design of alternative division units. For a given radix-b, the number of different algorithms of this kind is b/sup 2//4.

In this paper, we investigate the design of macrocell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE-754-1985 standard for binary floating-point numbers. The design and implementation of the generators rely on a powerful multi-view macroblock generator tool called GenOptim. This computer-aided design (CAD) tool is able to output a set of different descriptions for several VLSI technologies as well as field programmable gate arrays (FPGAs). The division and square root operators described in this paper use the signed-binary-digit representation. We start first by describing the operators for the significand, then we investigate the IEEE floating-point operators. Throughout this paper, and wherever appropriate, we present the implementation results using the GenOptim environment.

We present a dedicated integrated circuit for the simulation of charged particles based on Monte Carlo method. The Monte Carlo method leads to the solution of a particular form of the integro-differential Boltzmann equation (non-linear charge transport in semiconductors) permitting a direct statistical computation of the simulated particles distribution function in the phase space. This circuit should be the building block of a semiconductor device hardware simulator. Because of the complexity of microdynamical transport in semiconductors, the physical model used needs to be simplified in order to achieve a more simple circuit of small size. Starting from a chosen model we describe here how all the arithmetics involved in the problem has been set up for resolving the Boltzmann equation. Moreover, the binary format for the various physical quantities involved is discussed in view of the desired result accuracy: mainly, the drift velocity in a static uniform electric field taking into account all hot carrier effects.

Several systematic design approaches are known to be representatives of the techniques well adapted for testing sequential circuits (partial and full scan, LSSD...). However in some cases, like for the test of on-line operators, ad-hoc DFT (design for testability) schemes become more suitable. Indeed, on-line arithmetic are used for high precision numbers resulting on high length operators. Thus the length of a test sequence for a scan design approach can grow quite large due to the shift in (shift out) of test values (test responses) and therefore the test application time would become prohibitive. Moreover, the arithmetic nature of these operators imply that some errors detected locally are masked before their observation at the primary outputs. In this paper we describe an analytic approach for testing on-line multipliers that allows to avoid error masking without adding extra hardware for internal state observability while maintaining a 100% fault coverage. Compared to a DFT approach using parity trees, this method leads to a reduction of the area overhead from 7% to 1% and of the extra pins count from 6 to 3 in the case of the on-line multipliers considered in this paper.>

Experience has shown that generator programs are quite often written by VLSI designers, as they hold the empirical knowledge better than anyone. However, their ability does not necessarily include programming and debugging skills: these designers have to focus on the problem at hand not on the tools or the language they use to solve it. GenOptim has been created to quickly design efficient IEEE 754 floating-point macro-cell generators that do not rely on particular target technologies. Whereas the design of fast and efficient adders, multipliers and shifters is well understood division and square root remain a serious design challenge. GenOptim was used to quickly evaluate new divider architectures.>

Two pure combinational radix-4 digit-set converters for use in hybrid arithmetic are presented. The conventional to minimally redundant balanced signed-digit set converter is very simple and has zero cost and delay in terms of gates. The balanced to conventional digit-set converter performs the conversion "on the fly" with the generation of the balanced signed-digits, from the most significant to the least significant one; it has an O(1) delay (i.e. constant and independent of the length n of the number), an O(n/sup 2/) cost and a regular structure suitable for VLSI implementation. A review of the principles of hybrid addition/subtraction was previously presented (N. Takagi et al., 1985).>

This paper deals with the test of an integrated on-line multiplier suitable for very large numbers. Due to the serial structure of the circuit, the controllability and observability of the different elements are very low. In particular, an embedded sequential array cannot be accessed directly and has no primary outputs. Therefore, we propose here two DFT alternatives. The first one determines the most significant nodes to be considered in order to avoid error masking. The second approach increases the parallelism of the circuit and presents, thus, the advantage of a large reduction in the test duration. Both options have a low area overhead and a reduced number of extra pins.>

The authors present a new modular architecture for the online evaluation of power series. It can be used to quickly compute any function that can be approximated by the first terms of its Taylor expansion (i.e., most math functions). For trigonometric functions, the method matches Cordic-like methods and leads to more regular architectures. The authors also present a VLSI implementation of this architecture.>

We present some VLSI structures suitable for online arithmetic embedded algorithms using a radix-two fixed point signed digit system. As an application, we present online add/multiply architectures allowing the obtention of a zero-delay operator. An example of a circuit for online computation of several real functions using polynomials is also discussed.>

Various algorithms for finding the greatest common divisor (GCD) and extended GCD of very large integers are explored. In particular, the tradeoff between computation time and area is examined. Two of the algorithms, from which the method for deriving variants is straightforward, are detailed. Then the architecture of a VLSI processor dedicated to GCD as well as multiply, divide, square root, etc. of very large numbers (>600 decimal digits), using an internal radix 2 redundant representation and supporting multiple precision, is described.>

The authors deal with the detailed VLSI implementation of a fast bit-serial operator designed to perform very high precision (600 decimal digits) additions, multiplications, and divisions, and some of the applications of the circuit are discussed. Online arithmetic needs carry-free redundant number systems. Frequently, the radix chosen is different from 2, since a carry-free addition algorithm can be used in radix r not=2. In radix 2, carry-free addition is possible, but with two inconveniences: the algorithm seems more complicated, and the delay is larger. The authors show that the first inconvenience vanishes if good binary representation of the digits in radix-2 signed digit notation is chosen.>

We describe a general VLSI architecture for the computation of arithmetic expressions including floating-point trancendental functions. This architecture is divided in three parts: a communication machine, the control part of a computation machine and the operative part of this computation machine. In order to compute the most usual trancendental functions, we introduced some general algorithms, presented briefly here, including as a particular case the CORDIC scheme. Our major architecture goals were regularity, parametrization and automatic design. The final chip is designed in a 2-Alu CMOS technology, and its name is FELIN (“Fonctions ELémentaires INtégrées is the french for integrated elementary functions”). This work was supported in part by the GRECO C3and the GCIS of the French CNRS.

In this paper, we present a way to obtain efficient carry-skip adders, built with blocks of different sizes in VLSI technologies. We give some results about two-level carry-skip adders. We reduce our optimization problem to a geometrical problem, solved by means of an algorithm easily implemented on a microcomputer. Then we present an example of the realization of such an adder.