This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cells contain another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in a PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder.

To achieve higher degree of concurrency in a systolic array, it is desirable to make cells of a systolic array themselves a systolic array as well, leading to a structure called super-systolic array. This paper proposes a bit-level super-systolic FIR filter with a FPGA-based bit-serial semi-systolic multiplier. Compared to the word-level systolic FIR filter and corresponding super-systolic filter, the proposed design is very compact in that it needs only two 1-bit I/O ports in addition to significant improvement on hardware complexity. The input to the implementation proposed in this paper is a sequence of bit-string in contrast to the distributed arithmetic which assumes input of parallel bit-string. Also, the arrangement of the cells of a semi-systolic multiplier is tuned to fit to the structure of the FPGA. (This work was done as a part of Information & Communication fundamental Technology Research Program supported by Ministry of Information & Communication in republic of Korea.

High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The architecture of systolic array with its cells consisting of another systolic array is to be called super-systolic array.In this paper we propose a scalable super-systolic array architecture which shows high-performance and can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture.