This study introduces a novel Haptic Virtual Reality (HVR) simulator for intravenous (IV) needle insertion training, aiming to enhance traditional methods like manikins. Developed using a Meta Quest 2 headset, it incorporates two haptic devices: a haptic glove (SenseGlove Nova) for stabilization and a haptic stylus (Geomagic Touch) for needle insertion simulation, all integrated within Unity. A second prototype using a VR touch controller was created for user performance comparison. Both prototypes provide immersive experiences for hand-eye coordination and psychomotor skills. An evaluation experiment with 23 nursing students compared the systems to a previously developed Haptic Mixed Reality (HMR) version. Over three weeks, with three 10-minute training sessions, improvements in success rates and confidence were observed. The study included a Task Load Index assessment, indicating a manageable workload. Results suggest the HVR IV needle insertion simulator's potential to enhance nursing education.

Dematological skill training is essential for medical students to perform successful skin tumor surgery. However, there is no exisitng system that can provide high-quality tactile simulation and training as the substitute of clinical training with patients. In this study, we developed immersive haptic simulation combined with virtual reality for simulating two important dermatological skills, outlining and incision, and investigated the effectiveness of the developed system to be used as a training tool at clinic or school. In the evaluation study, professional (dermatologists, residents, medical students) and non-professional (students in computer science) groups of people were invited to test the developed system in terms of usability and efficacy of multimodal feedback (virtual graphic and haptic feedback). The evaluation results suggest that the training system has potential for high adoption, especially with haptic feedback in a virtual reality envrionment. The quantitative results based on a proposed metrics prove the ability of the training that discriminate experts from non-experts as well as objectively measure the dermatological skills.

In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency (fT) of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 × 48 cell field programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (fT1/4 825 GHz) having 100x less power consumption than conventional vertical HBTs.

Analogy and bioinspired design have demonstrated applicability as effective tools for innovation, but they can be very difficult to implement. One challenge faced by students and other novice designers is their lack of knowledge to base analogies on. This challenge is also faced by engineers making distant-domain analogies to biology. Other open research questions surround effective strategies for students attempting to implement analogies. When students seek analogies should potential analogues be presented one at a time or should multiple analogues be presented simultaneously (presentation format)? This study implements a 2×2 between-subject factorial design to further explore the impact of presentation format and students' perceived valuableness of passages. Impact is measured in terms of the quality, novelty, and variety of ideas generated. Two additional control conditions were also included, one with no passages and another with random passages. The results from this study have shown that quality is significantly affected by valuableness of passages, novelty is not affected by any factor, and variety is significantly affected by both factors.

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

This paper considers a design of signal constellations for trans-modulation (constellation rearrangement: CoRe) in a relay system with the multiple links in which the same signal is decoded-and-forwarded to the destination over N time slots, each assigned to the different relay node. Demonstrating that the minimal accumulated squared Euclidean distance (MASED) is not an ultimate design metric to minimize the bit error rate (BER), we choose the BER for the joint log-likelihood ratio (LLR) combining scheme as a design metric, so as to find bit-to-symbol mapping for the multiple relay links. To handle the prohibitive amount of computational complexity associated with an exhaustive search over enumeration of all possible mappings, which grows exponentially with the number of relay links, genetic algorithm is employed for searching for the sub-optimal bitto-symbol mappings in the multiple relay links. We show that a new type of CoRe design without the gray-mapping constraint is critical for warranting the LLR-combining gain over the multiple relay links, e.g., approximately 4 dB gain for 4 relay links at high SNR as compared to the CoRe design for hybrid ARQ.

The paper considers a hybrid ARQ (HARQ) scheme for a linear pre-coding-based closed-loop multiple-input multiple- output (MIMO) system, in which a pre-coding matrix is dynamically selected for every retransmission by taking into account a symbol-level combining gain obtained from the previous receptions. A new retransmission structure with a sequence of multiple codebooks is proposed that are optimized for combining gain, rather than using a single identical codebook for every retransmission. Furthermore, a criterion for selecting a pre-coding matrix for each retransmission can be provided so as to minimize the retransmission error probability. Under the proposed multiple codebook structure for MIMO-HARQ systems, a sequence of optimum codebooks is constructed for the subsequent retransmissions. Simulation results are presented for showing that the proposed scheme achieves significant error performance advantages over conventional schemes with a single codebook and furthermore, a near-optimal performance is achieved as the codebook size chosen is large enough.

While the conventional codebook is defined only for the initial transmission in the closed-loop MIMO system, this paper proposes a new retransmission structure with a sequence of multiple codebooks, rather than using a single identical codebook for every retransmission. The pre-coding matrices, in each codebook, are sequentially linked so that each one can be used for a sequential hybrid ARQ transmission attempt, without invoking any index feedback from the receiver. It has been shown that the proposed codebook structure provides a performance gain of more than 3 dB over the conventional scheme in the long-term static channel.

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.

Forty years ago Gene Amdahl published a figure of merit for parallel computation, which proved extremely controversial. The controversy still rages today, although those that have looked closely at this figure of merit conclude that it is correct, but perhaps misinterpreted. In this paper we will look at a small variation on that law that suggests computer designers should take a closer look at two emerging technologies, SiGe HBT BiCMOS and 3D chip stacking. We may be overlooking a way to continue the clock race, and in so doing accomplish better parallelism.