Demo Data from SIGIR 2026 / reviewers in the wild / expert
Jonathan A. Winter
dblp:97/1707
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorSecurity and privacy · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 54% Processor architecture and microarchitecture · 23% Parallel and multicore computing · 23% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › thermal management
dynamic thermal management |
0.1 | 1 | 2008 | Addressing thermal nonuniformity in SMT workloads · ACM Trans. Archit. Code Optim. 2008 |
Processor architecture and microarchitecture › multithreading
simultaneous multithreading |
0.1 | 1 | 2008 | Addressing thermal nonuniformity in SMT workloads · ACM Trans. Archit. Code Optim. 2008 |
Energy-efficient computing
thermal management |
0.1 | 1 | 2008 | Addressing thermal nonuniformity in SMT workloads · ACM Trans. Archit. Code Optim. 2008 |
Parallel and multicore computing › parallel programming runtimes
thread management |
0.1 | 1 | 2008 | Addressing thermal nonuniformity in SMT workloads · ACM Trans. Archit. Code Optim. 2008 |
Energy-efficient computing › voltage scaling
dynamic voltage scaling |
0.0 | 1 | 2008 | Addressing thermal nonuniformity in SMT workloads · ACM Trans. Archit. Code Optim. 2008 |
Methods — techniques the papers use, named apart from their topics
thread steering · 0.1DVS · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Scalable thread scheduling and global power management for heterogeneous many-core architecturesabstractFuture many-core microprocessors are likely to be heterogeneous, by design or due to variability and defects. The latter type of heterogeneity is especially challenging due to its unpredictability. To minimize the performance and power impact of these hardware imperfections, the runtime thread scheduler and global power manager must be nimble enough to handle such random heterogeneity. With hundreds of cores expected on a single die in the future, these algorithms must provide high power-performance efficiency, yet remain scalable with low runtime overhead. Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker |
PACT | 1 |
| 2008 | Scheduling algorithms for unpredictably heterogeneous CMP architecturesabstractIn future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ among the cores in an unanticipated manner. Under this scenario, naive assignments of applications to cores degraded by various faults and variations may result in large performance losses and power inefficiencies. We propose scheduling algorithms based on the Hungarian Algorithm and artificial intelligence (AI) search techniques that account for this future uncertainty in core characteristics. These thread assignment policies effectively match the capabilities of each degraded core with the requirements of the applications, achieving an ED2only 3.2% and 3.7% higher, respectively, than a baseline eight core chip multiprocessor with no degradation, compared to over 22% for a round robin policy. Jonathan A. Winter, David H. Albonesi |
DSN | 1 |
| 2008 | Addressing thermal nonuniformity in SMT workloadsabstractWe explore DTM techniques within the context of uniform and nonuniform SMT workloads. While DVS is suitable for addressing workloads with uniformly high temperatures, for nonuniform workloads, performance loss occurs because of the slowdown of the cooler thread. To address this, we propose and evaluate DTM mechanisms that exploit the steering-based thread management mechanisms inherent in a clustered SMT architecture. We show that in contrast to DVS, which operates globally, our techniques are more effective at controlling temperature for nonuniform workloads. Furthermore, we devise a DTM technique that combines steering and DVS to achieve consistently good performance across all workloads. Jonathan A. Winter, David H. Albonesi |
ACM Trans. Archit. Code Optim. | 1 |