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Vincent Néri

dblp:97/2814 · DBLP profile ↗
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8ranked-venue papers
1as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Distributed systems · 83% Parallel and multicore computing · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
fault tolerance
0.012002
MPICH-V: toward a scalable fault tolerant MPI for volatile nodes · SC 2002
Distributed systems › fault tolerance
message logging
0.012002
MPICH-V: toward a scalable fault tolerant MPI for volatile nodes · SC 2002
Distributed systems › fault tolerance
rollback recovery
0.012002
MPICH-V: toward a scalable fault tolerant MPI for volatile nodes · SC 2002
Parallel and multicore computing › MPI
fault-tolerant MPI
0.012002
MPICH-V: toward a scalable fault tolerant MPI for volatile nodes · SC 2002
Parallel and multicore computing
MPI
0.012002
MPICH-V: toward a scalable fault tolerant MPI for volatile nodes · SC 2002

Methods — techniques the papers use, named apart from their topics

uncoordinated checkpointing · 0.0distributed message logging · 0.0
YearPublicationVenuePosition
2007 Scalability Comparison of Four Host Virtualization Tools
Benjamin Quétier, Vincent Néri, Franck Cappello
J. Grid Comput.2
2006 Private Virtual Cluster: Infrastructure and Protocol for Instant Grids
Ala Rezmerita, Tangui Morlier, Vincent Néri, Franck Cappello
Euro-Par3
2005 Computing on large-scale distributed systems: XtremWeb architecture, programming models, security, tests and convergence with grid
Franck Cappello, Samir Djilali, Gilles Fedak, Thomas Hérault, Frédéric Magniette, Vincent Néri, Oleg Lodygensky
Future Gener. Comput. Syst.6
2003 XtremWeb & Condor sharing resources between Internet connected Condor pools
abstract
Grid computing presents two major challenges for deploying large scale applications across wide area networks gathering volunteers PC and clusters/parallel computers as computational resources: security and fault tolerance. This paper presents a lightweight Grid solution for the deployment of multi-parameters applications on a set of clusters protected by firewalls. The system uses a hierarchical design based on Condor for managing each cluster locally and XtremWeb for enabling resource sharing among the clusters. We discuss the security and fault tolerance mechanisms used for this design and demonstrate the usefulness of the approach measuring the performances of a multi-parameters bio-chemistry application deployed on two sites: University of Wisconsin/Madison and Paris South University. This experiment shows that we can efficiently and safely harness the computational power of about 200 PC distributed on two geographic sites.
Oleg Lodygensky, Gilles Fedak, Franck Cappello, Vincent Néri, Miron Livny, Douglas Thain
CCGRID4
2002 MPICH-V: toward a scalable fault tolerant MPI for volatile nodes
abstract
Global Computing platforms, large scale clusters and future TeraGRID systems gather thousands of nodes for computing parallel scientific applications. At this scale, node failures or disconnections are frequent events. This Volatility reduces the MTBF of the whole system in the range of hours or minutes. We present MPICH-V, an automatic Volatility tolerant MPI environment based on uncoordinated checkpoint/roll-back and distributed message logging. MPICH-V architecture relies on Channel Memories, Checkpoint servers and theoretically proven protocols to execute existing or new, SPMD and Master-Worker MPI applications on volatile nodes. To evaluate its capabilities, we run MPICH-V within a framework for which the number of nodes, Channels Memories and Checkpoint Servers can be completely configured as well as the node Volatility. We present a detailed performance evaluation of every component of MPICH-V and its global performance for non-trivial parallel applications. Experimental results demonstrate good scalability and high tolerance to node volatility.
George Bosilca, Aurelien Bouteiller, Franck Cappello, Samir Djilali, Gilles Fedak, Cécile Germain, Thomas Hérault, Pierre Lemarinier, Oleg Lodygensky, Frédéric Magniette, Vincent Néri, Anton Selikhov
SC11
2001 XtremWeb: A Generic Global Computing System
abstract
Global computing achieves high throughput computing by harvesting a very large number of unused computing resources connected to the Internet. This parallel computing model targets a parallel architecture defined by a very high number of nodes, poor communication performance and continuously varying resources. The unprecedented scale of the global computing architecture paradigm requires us to revisit many basic issues related to parallel architecture programming models, performance models, and class of applications or algorithms suitable for this architecture. XtremWeb is an experimental global computing platform dedicated to provide a tool for such studies. The paper presents the design of XtremWeb. Two essential features of this design are multi-applications and high-performance. Accepting multiple applications allows institutions or enterprises to set up their own global computing applications or experiments. High-performance is ensured by scalability, fault tolerance, efficient scheduling and a large base of volunteer PCs. We also present an implementation of the first global application running on XtremWeb.
Gilles Fedak, Cécile Germain, Vincent Néri, Franck Cappello
CCGRID3
1993 Balanced Distributed Memory Parallel Computers
abstract
Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
ICPP (1)6
1993 Hardware features of the static communication network of a parallel architecture
Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
Microprocess. Microprogramming1