Demo Data from SIGIR 2026 / reviewers in the wild / expert
Masahiro Miwa
dblp:97/5185
· DBLP profile ↗
6ranked-venue papers
3as first author
2since 2021 · last 2026
0009-0001-5739-0666ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Efficient and distributed learning · 50% Transfer learning and domain adaptation · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 77% GPUs and heterogeneous computing · 23% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Transfer learning and domain adaptation › model adaptation
batch normalization adaptation |
0.4 | 1 | 2020 | An Efficient Technique for Large Mini-batch Challenge of DNNs Training on Large Scale Cluster · HPDC 2020 |
Machine learning › Efficient and distributed learning › large-scale learning › scalable training
large mini-batch training |
0.4 | 1 | 2020 | An Efficient Technique for Large Mini-batch Challenge of DNNs Training on Large Scale Cluster · HPDC 2020 |
Parallel and multicore computing
distributed deep learning training |
0.4 | 1 | 2020 | An Efficient Technique for Large Mini-batch Challenge of DNNs Training on Large Scale Cluster · HPDC 2020 |
Methods — techniques the papers use, named apart from their topics
hyperparameter tuning · 0.9final polishing · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Performance Characterization of LLM Inference under Limited GPU Resources
Madoka Takato, Akira Hirai, Reika Kinoshita, Masahiro Miwa, Masato Oguchi |
COMPSAC | 4 |
| 2021 | Towards Straggler-Tolerant and Accuracy-Aware Distributed DNN Training in CloudsabstractThis study investigated how straggler mitigation affects accuracy during distributed training. While distributed training is one promising way to shorten training time, we cannot obtain a maximum performance improvement if some workers become stragglers due to a slowdown. We can avoid the performance impact from stragglers by excluding them from training. However, we face another problem of decreasing accuracy during training because gradients computed by excluded stragglers are not reflected in the training. To achieve both straggler tolerance and accuracy awareness, we should implement distributed training so that excluded stragglers return to the training once they recover from slowdown. Although some implementations supporting auto-scaling have been created, they have not evaluated the training accuracy during scale-in to exclude stragglers from training and scale-out to return them to training. Therefore, we conducted experiments to see how excluding stragglers causes accuracy degradation. We also discussed how the exclusion time and training data assignment can have an impact on accuracy during training. Shingo Okuno, Masahiro Miwa, Naoto Fukumoto |
CCGRID | 2 |
| 2020 | An Efficient Technique for Large Mini-batch Challenge of DNNs Training on Large Scale ClusterabstractDistributed deep learning using large mini-batches is a key strategy to perform the deep learning as fast as possible, but it represents a great challenge as it is difficult to achieve high scaling efficiency when using large clusters without compromising accuracy. The particular problem in this challenge is decreasing the number of model update iterations in whole of training. Thus, we need a technique which can converge the validation accuracy with a small number of iterations to address this challenge. In this paper, we introduce a novel technique, Final Polishing. This technique adjusts the means and variances in the batch normalization and mitigates the difference of normalization between validation datasets and augmented training datasets. By applying the technique, we achieved top-1 validation accuracy of 75.08% with mini-batch size of 81,920, with 2,048 GPUs and completed the training of ResNet-50 in 74.7 seconds.In addition, targeting top-1 validation accuracy of 75.9% or more, we tried additional parameters tuning. Then, we adjusted the number of GPUs and hyperparameters of DNNs with Final Polishing, and we also achieved top-1 validation accuracy of 75.97% with mini-batch size of 86,016, with 3,072 GPUs and completed the training of ResNet-50 in 62.1 seconds. Akihiko Kasagi, Akihiro Tabuchi, Masafumi Yamazaki, Takumi Honda, Masahiro Miwa, Naoto Fukumoto, Tsuguchika Tabaru, Atsushi Ike, Kohta Nakashima |
HPDC | 5 |
| 2015 | Progression of MPI Non-blocking Collective Operations Using Hyper-ThreadingabstractMPI non-blocking collective operations offer a high level interface to MPI library users, and potentially allow communication to be overlapped with calculation. Progression, which controls communications running in the background of the calculation, is the key factor to achieve an efficient overlap. The most commonly used progression method is manual progression, in which a progression function is called in the main calculation. In manual progression, MPI library users have to estimate the communication timing to maximize the overlap effect and thus to manage the complex communication optimization. An alternative approach for progression is the use of separate communication threads. By using communication threads, communication calculation overlap can be achieved simply. However, context switches between the calculation thread and the communication thread cause lower performance in the frequent case where all cores are used for calculation. In this paper, we propose a novel threaded progression method using Hyper-Threading to maximize the overlap effect of non-blocking collective operations. We apply MONITOR/MWAIT instructions to the communication thread on Hyper-Threading so as not to degrade the calculation thread due to shared core resource conflict. Evaluation on 8-node Infini Band connected IA server clustered systems confirmed that the latency is suppressed to a small level and that our approach has an advantage over manual progression in terms of communication-calculation overlap. Using a real application of CG benchmark, our method achieved 32% reduction in execution time compared to using blocking collective operation, and that is nearly perfect overlap. Although manual progression also achieved perfect overlap, our method has the advantage that no communication timing tuning is required for each application. Masahiro Miwa, Kohta Nakashima |
PDP | 1 |
| 2013 | Interference-aware Incoming Message Detection for MPI Threaded ProgressionabstractTo enable overlap of computation and communication with non-blocking collective communication, it is required to progress asynchronously a sequence of communications. One of the naive implementation is to use a separate thread for communitation and run it in back of computation thread. However if the total number of threads is greater than the number of physical cores, context switches cause performance degradation of the computation thread. Simultaneous MultiThread (SMT) can be used to avoid this problem. However, commonly-used busy polling for incoming message detection also causes performance degradation of the computation thread. In this paper, we propose incoming message detection method using MONITOR/MWAIT instructions to reduce the performance degradation. Experiment results show that the performance of computation thread is improved largely compared to the busy polling method while latency is suppressed by a small increase. Masahiro Miwa, Kohta Nakashima, Akira Naruse |
CCGRID | 1 |
| 2001 | CMAC modeling using pseudo-bacterial genetic algorithm and its accelerationabstractA cerebellar model arithmetic computer (CMAC) is a neural network whose advantage is fast learning. It is, however, difficult to decide on the various parameters of a CMAC in advance. The pseudo-bacterial genetic algorithm (PBGA) is an evolutionary algorithm that is efficient in local searching. This paper proposes a "PBGA/CMAC" system that decides the positions of partitions, which are the main parameters of a CMAC, using the PBGA. The PBGA/CMAC hardware is implemented for acceleration, because PBGA/CMAC needs a large amount of computation time. An efficient learning method using pipelining is also presented. It is found that the accuracy with the proposed learning method is almost the same as that of the conventional CMAC's learning. The PBGA/CMAC hardware is 140 times faster than that of the equivalent PBGA software. Masahiro Miwa, Takeshi Furuhashi, Motoaki Matsuzaki, Shigeru Okuma |
SMC | 1 |