In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.

The paper introduces a new monitoring circuit to quantify the change in performance of devices undergoing NBTI stress at 65nm technology node. The proposed solution consists of a pMOS device experiencing accelerated NBTI stress, a Capacitive Switch, Relaxation Oscillator structure, serving as a monitoring unit, which allows to dynamically track the NBTI-induced degradation with time. The circuit measures the change of the relaxation frequency which is attributed to the saturation current shift in pMOSFET due to NBTI stress. The proposed circuit with counting unit produces a digital output which makes it easier to collect. The capacitive relaxation oscillator modeling has been established and verified by the experiments. Meanwhile, the circuit is easily to be integrated with the digital logic system. Based on the device matrix, the effect of initial saturation current distribution and NBTI-induced time-dependent variability can also be obtained.