Demo Data from SIGIR 2026 / reviewers in the wild / expert
Yen-Chuen Wei
dblp:98/3378
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
circuit partitioning |
0.0 | 2 | 1991 | Ratio cut partitioning for hierarchical designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 An improved two-way partitioning algorithm with stable performance [VLSI] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Electronic design automation
physical design |
0.0 | 2 | 1991 | Ratio cut partitioning for hierarchical designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 An improved two-way partitioning algorithm with stable performance [VLSI] · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Electronic design automation › physical design › circuit partitioning
ratio-cut partitioning |
0.0 | 1 | 1991 | Ratio cut partitioning for hierarchical designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991 |
Methods — techniques the papers use, named apart from their topics
multicommodity flow · 0.0linear programming · 0.0kernighan-lin · 0.0heuristic algorithm · 0.0clustering · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | An improved two-way partitioning algorithm with stable performance [VLSI]abstractA two-way partitioning algorithm is presented that significantly improves on the highly unstable results typically obtained from the traditional Kernighan-Lin-based algorithms. The algorithm groups highly connected components into clusters and rearranges the clusters into two final subsets with specified sizes. It is known that the grouping operations reduce the complexity, and thus improve the results, of partitioning very large circuits. However, if the grouping is inappropriate, the partitioning results may degenerate. To prevent degeneration, a ratio cut approach is used to do the grouping. By a series of experiments based on the tradeoff between cut weight and CPU time, the value which controls the resultant number of groups is determined. Good experimental results have been observed for cut weight and CPU time.> Chung-Kuan Cheng, Yen-Chuen Wei |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1991 | Ratio cut partitioning for hierarchical designsabstractCircuit partitioning for hierarchical VLSI design is addressed. A partitioning approach called ratio cut is proposed. It is demonstrated that the ratio cut algorithm can locate the clustering structures in the circuit. Finding the optimal ratio cut is NP-complete. However, in certain cases the ratio cut can be solved by linear programming techniques via the multicommodity flow formulation. Also proposed is a fast heuristic algorithm running in linear time with respect to the number of pins in the circuit. Experiments show good results in all tested cases.> Yen-Chuen Wei, Chung-Kuan Cheng |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1990 | A Two-Level Two-Way Partitioning AlgorithmabstractA two-way partitioning algorithm is presented which significantly improves on the highly unstable results from the traditional Kernighan-Lin based algorithms. The algorithm groups strongly connected components into clusters, and rearranges the clusters into two final subsets with specified sizes. It is known that the grouping operations reduce the complexity and thus improve the results of partitioning very large circuits. However, if the grouping is inappropriate, the partitioning results may degenerate. To prevent degeneration, the authors use a ratio cut approach to do the grouping. By a series of experiments based on the tradeoff between cut capacity and CPU time, the authors determine an optimal value to control the resultant number of groups. Good experimental results have been observed in terms of cut capacity and CPU time.> Yen-Chuen Wei, Chung-Kuan Cheng |
ICCAD | 1 |
| 1989 | Towards efficient hierarchical designs by ratio cut partitioningabstractA partitioning approach called ratio cut is proposed. The authors demonstrate that the ratio cut algorithm can locate the clustering structures in the circuit. Finding the optimal ratio cut is NP-complete. However, in certain cases the ratio cut can be solved by linear programming techniques via the multicommodity flow problem. They also propose a fast heuristic algorithm running in linear time with respect to the number of pins in the circuit. Experiments show good results in all tested cases, and as much as 70% improvement over the Kernighan-Lin algorithm in terms of the proposed ratio metric.> Yen-Chuen Wei, Chung-Kuan Cheng |
ICCAD | 1 |