Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Panagiotis Stratis

dblp:98/3462 · DBLP profile ↗
← Back
5ranked-venue papers
4as first author
0since 2021 · last 2018
0000-0002-0426-8800ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Concurrent programming · 77% Compilers and program optimization · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming › memory models
test suite optimization
0.212016
Test case permutation to improve execution time · ASE 2016
Compilers and program optimization
code layout optimization
0.112016
Test case permutation to improve execution time · ASE 2016

Methods — techniques the papers use, named apart from their topics

cache locality optimization · 0.2
YearPublicationVenuePosition
2018 Assessing the Effect of Device-Based Test Scheduling on Heterogeneous Test Suite Execution
abstract
As software takes on more responsibility, it gets increasingly complex, requiring an extremely large number of tests for effective validation. This problem is more serious in heterogeneous system testing, where an application is required to be tested against a diverse collection of processors before is accepted for release.
Panagiotis Stratis, Gordon Brown
EASE1
2018 Assessing the effect of data transformations on test suite compilation
abstract
Background. The requirements and responsibilities assumed by software has increasingly rendered it to be large and complex. Testing to ensure that software meets all its requirements and is free from failures is a difficult and time-consuming task that necessitates the use of large test suites, containing many tests. Large test suites result in a corresponding increase in the size of the test code that sets up, exercises and verifies the tests. Time needed to compile and optimise the test code becomes prohibitive for large test code sizes.
Panagiotis Stratis, Vanya Yaneva, Ajitha Rajan
ESEM1
2018 Speeding up test execution with increased cache locality
abstract
Summary As the scale and complexity of software increases, the number of tests needed for effective validation becomes extremely large. Executing these large test suites is expensive, both in terms of time and energy. Cache misses are a significant contributing factor to execution time of software. We propose an approach that helps order test executions in a test suite in such a way that instruction cache misses are reduced. We also ensure that the approach scales to large test suite sizes. We conduct an empirical evaluation with 20 subject programs and test suites from the SIR repository, EEMBC suite, and LLVM Symbolizer, comparing execution times and cache misses with test orderings maximising instruction locality versus a traditional ordering maximising coverage and random permutations. We also assess overhead of algorithms in generating the orderings that optimise cache locality. Nature of programs and tests impact the performance gained with our approach. Performance gains were considerable for programs and test suites where the average number of different instructions executed between tests was high. We achieved an average execution speedup of 6.83% and a maximum execution speedup of 17% over subject programs with differing control flow between test executions.
Panagiotis Stratis, Ajitha Rajan
Softw. Test. Verification Reliab.1
2016 A Study on the Influence of Software and Hardware Features on Program Energy
abstract
Software energy consumption has emerged as a growing concern in recent years. Managing the energy consumed by a software is, however, a difficult challenge due to the large number of factors affecting it -- namely, features of the processor, memory, cache, and other hardware components, characteristics of the program and the workload running, OS routines, compiler optimisations, among others. In this paper we study the relevance of numerous architectural and program features (static and dynamic) to the energy consumed by software. The motivation behind the study is to gain an understanding of the features affecting software energy and to provide recommendations on features to optimise for energy efficiency.
Ajitha Rajan, Adel Noureddine, Panagiotis Stratis
ESEM3
2016 Test case permutation to improve execution time
abstract
With the growing complexity of software, the number of test cases needed for effective validation is extremely large. Executing these large test suites is expensive, both in terms of time and energy. Cache misses are known to be one of the main factors contributing to execution time of a software. Cache misses are reduced by increasing the locality of memory references. For a single program run, compiler optimisations help improve data locality and code layout optimisations help improve spatial locality of instructions. Nevertheless, cache locality optimisations have not been proposed and explored across several program runs, which is the case when we run several test cases.
Panagiotis Stratis, Ajitha Rajan
ASE1