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Tai A. Ly

dblp:98/6136 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Electronic design automation · 86% Cloud and datacenter computing · 10% Integrated circuit design · 4%

Topics — the 6 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.031993
Applying simulated evolution to high level synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Bottom Up Synthesis Based on Fuzzy Schedules · DAC 1991
A Generalized Interconnect Model for Data Path Synthesis · DAC 1990
Electronic design automation › high-level synthesis
scheduling and allocation
0.011993
Applying simulated evolution to high level synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Cloud and datacenter computing › resource allocation › resource mapping
resource allocation and binding
0.011991
Bottom Up Synthesis Based on Fuzzy Schedules · DAC 1991
Electronic design automation › high-level synthesis
data path synthesis
0.011990
A Generalized Interconnect Model for Data Path Synthesis · DAC 1990
Electronic design automation › physical design
interconnect synthesis
0.011990
A Generalized Interconnect Model for Data Path Synthesis · DAC 1990
Electronic design automation
physical design
0.011990
A Generalized Interconnect Model for Data Path Synthesis · DAC 1990

Methods — techniques the papers use, named apart from their topics

simulated evolution · 0.0probabilistic hill climbing · 0.0fuzzy set theory · 0.0dynamic interconnect allocation · 0.0smalltalk · 0.0model-view-controller · 0.0
YearPublicationVenuePosition
1993 Applying simulated evolution to high level synthesis
abstract
A general optimization algorithm known as simulated evolution (SE) is applied to the tasks of scheduling and allocation in high level synthesis. Basically, SE-based synthesis explores the design space by repeatedly ripping up parts of a design in a probabilistic manner and reconstructing them using application-specific heuristics that combine rapid design iterations and probabilistic hill climbing to achieve effective design space exploration. Benchmark results are presented to demonstrate the effectiveness of this approach. The results of a number of experiments that provide insight into why SE-based synthesis works so well are given.>
Tai A. Ly, Jack T. Mowchenko
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1991 Bottom Up Synthesis Based on Fuzzy Schedules
abstract
In this paper, we present a new bottom up synthesis formulation designed for full allocation of data path o~rations and data values prior to scheduling.This work is novel because it treats unscheduled operations as having uncertain schedules, then applies fuzzy set theQry to quantify these uncertainties during allocation.This formulation has been implemented in a simulated evolution based synthesis system, and experimental results are presented to demonstrate the strength of this approach.
Tai A. Ly, Jack T. Mowchenko
DAC1
1990 A Generalized Interconnect Model for Data Path Synthesis
abstract
A generalized interconnect model for data path synthesis is presented. This is a multi-level interconnect model designed for synthesis under interconnect constraints. Two novel algorithms for dynamic interconnect allocation and interconnect synthesis are also described. These algorithms help implement the generalized interconnect model in the Elf hardware compiler.
Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc
DAC1
1988 Constraint Propagation in an Object-Oriented IC Design Environment
Tai A. Ly, Emil F. Girczyc
DAC1
1987 STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct
abstract
STEM (SmallTalk Environment of Module design) is an IC design environment written in Smalltalk aimed at integrating design automation tools with manual design. STEM is based on the Smalltalk model-view-controller concept. Each cell in the database is represented by a single Smalltalk class. This serves as the “model” and encapsulates all (permanent) information about the cell. Different design representations of the single model are achieved by calculating views which are strictly temporary. All views of an object are linked to the model. This allows views to be updated whenever a change in the model's state is detected, and prevents permanent aliases of data. Design changes are entered using a Smalltalk controller attached to the model.
Emil F. Girczyc, Tai A. Ly
DAC2