Double Patterning Technology (DPT) conflicts express themselves as odd cycles of spacing between layout shapes. One way of resolving these is by imposing a large spacing constraint between a pair of shapes participant in an odd cycle. However, this may shrink spacing in other parts of the layout and introduce DRC violations or new DPT conflicts. In this work, we model DPT conflict resolution as a constrained linear optimization problem, look ahead to upfront estimate potential violations and preclude them with additional constraints. We borrow the approach of Satisfiability Modulo Theory (SMT) solvers to simultaneously check satisfiability of linear constraint set and resolution of DPT conflicts. These two are interleaved and feed information to each other to churn out a feasible set of constraints that fixes DPT and DRC violations. We demonstrate the efficacy of the method on layouts at advanced nodes.

Traditionally, automatic design rule correction (DRC) problem is modeled as a Linear Program (LP) with design rules as difference constraints under minimum perturbation objective. This yields Totally Uni-Modular (TUM) constraint matrices thereby guaranteeing integral grid-compliant solutions with LP solvers. However, advanced technology nodes introduce per-layer grids or discrete tracks that result into non-TUM constraint matrices for the DRC problem. Consequently, LP solvers do not guarantee integral solutions. In this work, we propose a novel formulation using an 'un-rolling' technique. Our formulation guarantees TUM constraint matrices and hence integral multiple grid/track compliant solutions. We demonstrate its efficacy on layouts at advanced nodes.

Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors. The design of such specialized processors requires software development tools such as simulators and compilers. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). In this paper, we present the Mescal Architecture Description Language (MADL). MADL features a two-layer structure, a core layer and an annotation layer. The core layer is based on a formal and flexible microprocessor model -- the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range of architectures. We address the challenges faced in designing the core layer to combine the OSM model with techniques for achieving compact processor descriptions. The annotation layer features a generic syntax that allows creating annotation schemes to specify implementation dependent or tool specific information. To show the effectiveness of MADL, we present an MADL-based simulator synthesis framework that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort. We also describe our annotation schemes that enable the extraction of architecture properties for use in instruction scheduling and integer-linear-programming based register allocation. Our experimental results demonstrate the efficacy of MADL as a practical and promising language for the development of programmable platforms.

A standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the different types of processing elements with efficiency measured in terms of power, area, and execution time. In addition, the compilers should also be highly retargetable to enable the system designer to quickly evaluate different cores for the application on hand and reduce the time to market. In this paper, we show that we can extend a conventional VLIW compilation environment to develop highly retargetable optimizing compilers for DSPs with irregular architectures. We have used the second generation Fujitsu Hiperion fixed-point DSP as our primary example to evaluate the compiler framework. We demonstrate through experimental results that execution time for the assembly code generated using our framework is roughly two times better than that of the code generated by a widely used commercially available DSP compiler. Even without incorporating DSP-specific optimizations in our extended VLIW framework, we demonstrate that the compiled code has a better performance than the code generated by a commercial DSP-specific compiler in all our examples.

Article Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints Share on Authors: Subramanian Rajagopalan Department of Electrical, Engineering, Princeton University, Princeton, NJ Department of Electrical, Engineering, Princeton University, Princeton, NJView Profile , Manish Vachharajani Department of Electrical, Engineering, Princeton University, Princeton, NJ Department of Electrical, Engineering, Princeton University, Princeton, NJView Profile , Sharad Malik Department of Electrical, Engineering, Princeton University, Princeton, NJ Department of Electrical, Engineering, Princeton University, Princeton, NJView Profile Authors Info & Claims CASES '00: Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systemsNovember 2000 Pages 157–164https://doi.org/10.1145/354880.354902Online:01 November 2000Publication History 24citation161DownloadsMetricsTotal Citations24Total Downloads161Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access