Deep learning-based joint source-channel coding (DeepJSCC) has shown significant benefits in emerging semantic and task-oriented communications, providing a promising solution for reducing latency and bandwidth requirements in next-generation mobile networks. However, its deployment on resource-constrained devices is limited by model complexity. Devices with varying computational capacities require models of distinct architectures and complexity levels, motivating the design of a cross-architecture model compression scheme for DeepJSCC. In this paper, we propose a cross-architecture knowledge distillation framework called CAKDJSCC for heterogeneous DeepJSCC models. Specifically, we design a teaching assistant network with feature fusion modules (FFMs) that dynamically perceive architecture gaps between teacher and student models, thereby generating student-adaptive feature representations to alleviate feature space misalignment caused by architectural inconsistencies. In addition, we introduce a conditional information bottleneck (CIB) loss to optimize the distillation process, which prevents students from overfitting to teacher-specific inductive biases while enhancing knowledge transfer efficiency in cross-architecture scenarios. Extensive experiments demonstrate that our approach significantly improves the student model's reconstruction accuracy and perceptual quality without increasing the inference latency while minimizing the performance degradation during model compression.

In this work, the goal is to develop a flexible CAD tool by which designers can explore integration of different types of embedded hard cores and interfaces in the FPGA architectures. Our tool takes a RTL design and defined embedded hard cores. The authors have modified VPR for place and route with embedded blocks. We have experimented different modules to be embedded as hard cores on a FPGA device. We also explore the FPGA routing architecture with embedded hard cores by applying uniform and non-uniform routing channels. In many cases, non-uniform channels produce more area-efficient architectures. Our results show that there is a need for a tool for better exploration of design space for FPGAs with embedded hard cores