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Stylianos D. Pezaris

dblp:99/954 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1971
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design		 0.011971
A 40-ns 17-Bit by 17-Bit Array Multiplier · IEEE Trans. Computers 1971
Integrated circuit design › digital circuit design › arithmetic circuit design
array multiplier		 0.011971
A 40-ns 17-Bit by 17-Bit Array Multiplier · IEEE Trans. Computers 1971
Integrated circuit design › digital arithmetic circuits › integer multiplier
high-speed multiplier		 0.011971
A 40-ns 17-Bit by 17-Bit Array Multiplier · IEEE Trans. Computers 1971
Processor architecture and microarchitecture
arithmetic unit		 0.011971
A 40-ns 17-Bit by 17-Bit Array Multiplier · IEEE Trans. Computers 1971

Methods — techniques the papers use, named apart from their topics

gated adder circuit · 0.0carry anticipation · 0.0
YearPublicationVenuePosition
1971 A 40-ns 17-Bit by 17-Bit Array Multiplier
abstract
A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. The propagation of sum and carry signals is such that sum delays do not significantly contribute to the overall multiplier delay.
Stylianos D. Pezaris
 IEEE Trans. Computers1