In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clkdriver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clksignal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

In this paper we introduce a new flip-flop for use in a low- swing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flip-flop (LS-DCCFF) operates with a low-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed flip-flop was verified at extreme corners through simulations with parasitics extracted from layout. The LS-DCCFF enables 6.5% reduction in power compared to the full- swing flip-flop with 19% area overhead. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low-swing sinusoidal clock has been characterized. The LS-DCCFF has 870 ps longer data to output delay as compared to the full-swing flip-flop at the same setup time for a 100 MHz sinusoidal clock. The functionality of the proposed flip-flop was tested and verified by using the LS-DCCFF in a dual-mode multiply and accumulate (MAC) unit fabricated in TSMC 90-nm CMOS technology. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead for the MAC.

Lowering the supply voltage of static random access memories (SRAMs) during standby modes is an effective technique to reduce their leakage power consumption. To maximize leakage reductions, it is desirable to reduce the supply voltage as much as possible. SRAM cells can retain their data down to a certain voltage, called the data-retention voltage (DRV). Due to intra-die variations in process parameters, the DRV of cells differ within a single memory die. Hence, the minimum applicable standby voltage to a memory die (VDDLmin) is determined by the maximum DRV among its constituent cells. On the other hand, inter-die variations result in a die-to-die variation ofVDDLmin. Applying an identical standby voltage to all dies, regardless of their correspondingVDDLmin, can result in the failure of some dies, due to data-retention failures (DRFs), entailing yield losses. In this work, we first show that the yield losses can be significant if the standby voltage of SRAMs is reduced aggressively. Then, we propose a postsilicon standby voltage tuning scheme to avoid the yield losses due to DRFs, while reducing the leakage currents effectively. Simulation results in a 45-nm predictive technology show that tuning standby voltage of SRAMs can enhance data-retention yield by 10%-50%.

In this paper, design space exploration methods for interconnect repeaters in DSM power-managed VLSI are proposed. These methods guarantee that the designed interconnects are energy-optimal, while they meet their performance objectives in all the system operating states. These methods take the dynamic output resistance characteristic of the repeaters into account, when the system operating voltage and/or operating frequency requirement changes. Utilizing the proposed design methods, a multi-cycle bus is designed for some performance targets. HSPICE simulations confirm that the designed bus is energy-optimal, and it meets its performance objectives in all the system operating states.

Dynamic Voltage Scaling (DVS) is a successful design solution that addresses the challenges associated with low-power/energy and high-performance design in Deep Sub Micron (DSM) CMOS. In DSM, VLSI systems have become interconnect-centric; correspondingly, the associated design solutions should be adapted to preserve their functionality. In reference to this concern, and with respect to DVS, we propose a DVS scheme that takes interconnect effects into account. The proposed DVS scheme is a generalization of existing methods that treat systems as pure logic. To support this DVS scheme, two design metrics are introduced. These metrics model the performance of system components subject to DVS, based on the proportion of their delay due to interconnects. Based on the proposed design metrics, a compact delay model and a method for supply voltage selection are proposed. The limit of scaling for hazard-free system operation in VLSI systems is further formulated. It is shown that this limit can be smaller than the one dictated by the process technology. The proposed DVS scheme is applied to a 4-section global clock distribution network. Reported results show that this scheme improves both the timing accuracy and energy consumption aspects of DVS by 25% and 30% on average, respectively.

Employing microsystems with Dynamic Voltage Scaling (DVS) is an effective design solution to alleviate their energy consumption. The importance of such design technique keeps growing as both high-performance and low-energy consumption are simultaneously desirable. Existing Power Management Units (PMUs) that support DVS, mainly rely on the delay models valid for CMOS logic. In this work, we show that this may result into improper design and utilization of microsystems subject to DVS; as interconnect delay has become the dominant fraction of the total delay. In accordance with this design concern, we propose a modified delay model which encompasses the effect of interconnect parasitic components, and is suitable for accurate modeling, design and execution of DVS performed by PMUs in nanometer (nm) technologies. HSPICE simulations confirm that the proposed delay model is much more accurate when predicting the performance of a 4-section global H-Tree clock distribution network subject to voltage scaling. The error on predicted performance from true delays is reduced by up to a factor of 4.

New low power architecture for floating point adders is presented. The method is further enhanced by the introduction of pipelining. These two architectures together with the standard Floating Point Adder form the basis for development of a CAD tool for generating VHDL codes for Scalable Floating Point adders. The user interface is designed using C++ to give the user the choice of different Floating Point Adders (FADD) and the adding precision. The CAD tool then selects the appropriate FADD and generates a synthesizable VHDL code, corresponding to the selected FADD and the precision values entered by the user. Thus an architecture corresponding to a low delay or low power or low area can be selected. The architectures conform to IEEE 754 standard.

Clock uncertainty is a major concern in current high performance clock network design. A differential clocking scheme provides noise immunity and can address this challenge. In this paper, a differential line equivalent delay model is proposed to obtain zero skew differential clock networks. The method is applied to various benchmarks. On average, 97% skew reduction is obtained compared to the solution derived with the classic Elmore model. To improve performance of zero skew differential clock networks, differential buffers based on dynamic threshold transistors are proposed. Incorporation of proposed buffers to low swing zero skew differential clock network shows 25% delay improvement compared to conventional buffers. Moreover, the incorporation of proposed design methods shows 25% and 6% skew variations reduction in presence of power supply variations and crosstalk noise respectively, compared to low swing single-node clock distribution networks.

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMC's 0.13-/spl mu/m and TSMC's 0.18-/spl mu/m technologies, the model has an average error of 4.5% and a maximum error of 15%.

The need for incremental algorithms to implement engineering changes (ECs) in clock trees (CTs) is critical in the system-on-a-chip (SoC) design cycle. An algorithm, called adaptive wire adjustment (AWA), is proposed to minimize the clock skew iteratively to any given bound. In order to speed up AWA's convergence, a local topology-modification (LTM) technique is incorporated into AWA. Moreover, LTM incorporation into AWA results in total wire-length reduction as well. Also, the incorporation of the LTM technique into the deferred-merge embedding (DME) algorithm and Greedy-DME (GDME) helps reduce the total wire length by around 7.8% and 9.8%, respectively. Additionally, applying LTM to GDME reduces wire elongations and the standard deviation of the path lengths (SDPL) between clock pins by 96.4% and 51.5%, respectively.

We propose a new modulo arithmetic theorem to decompose the base of modulo operations. This new theorem has been used to reduce further the modulo size of the modified CRT (Chinese remainder theorem) for general moduli sets. Furthermore, we have applied the modulo decomposition technique and the modulo improved CRT to derive a R/B (residue-to-binary) converter algorithm for a newly found three-moduli set, M={2/sup n/-1,2/sup n/, 2/sup n-1/-1}. In comparison to the modified CRT, the improved CRT can cut the modulo size by half and reduce the length of the modulo operator in terms of 36%.

In this paper, we suggest an adaptive approach for the Clock Distribution Network (CDN) to cope with a modification in the VLSI system design. The CDN's wires are adjusted iteratively to reduce the skew that is resulting from a minor modification in the clock pins of a complex VLSI system. Such skew can be remedied by selecting a Balancing Node (BN) and adjust its edges so that the skew gets smaller. The required edge adjustments are determined using the Elmore delay model. The performance of the algorithm is investigated using different random sets of clock pins. Also, the algorithm is tested by altering some clock pins in a zero skew CDN. For small modifications in a large number of nodes in the CDN, our algorithm can achieve zero skew with less iterations than linear order algorithms.

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters, taking into account the main effects of deep submicron (DSM) such as velocity saturation and mobility degradation. The relationship between the input and output transitions is discussed and captured by a closed-form expression. Also, this model has been formulated to depend only on SPICE parameters that are usually provided with the given technology. In other words, neither presimulated extracted parameters nor fitting parameters are required. Thus, the developed model is technology-portable. The proposed model is validated by comparing its results with Spectre simulation results. To ensure the model's robustness, a wide range of output loading and input transition times have been considered. Also, to ensure the model's portability and accuracy for DSM devices, 0.25, 0.18, and 0.13-/spl mu/m technologies have been used to conduct our comparison. Considering the mentioned technologies, the proposed model achieved less than 10% error when it is compared to Specter level 11 (BSIM3v3) simulation results.

We present a new architecture of a low power floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, controlled data paths allows activity reduction. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipation logic as well as data path simplifications. The proposed scheme offers a 10/spl times/ reduction in power consumption in comparison to that of conventional high speed floating point adders that use leading zero anticipation logic, for IEEE single precision floating point data format. The reduction in power delay product is about 16/spl times/. The corresponding figures for double precision units are around 40/spl times/ and 66/spl times/ respectively.

Article Free Access Share on Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition Authors: R. V. K. Pillai Concordia University, Montreal, Canada Concordia University, Montreal, CanadaView Profile , D. Al-Khalili Concordia University, Montreal, Canada Concordia University, Montreal, CanadaView Profile , A. J. Al-Khalili View Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 235–238https://doi.org/10.1145/263272.263341Published:01 August 1997Publication History 6citation138DownloadsMetricsTotal Citations6Total Downloads138Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations.Radix 4 Modified Booth Algorithm (MBA) is currently the most popular choice for partial product reduction in parallel multipliers although 4:2 compressors can also produce equivalent results.Our energy delay analysis of these two schemes taking into account the architectural as well as circuit implementation issues suggests the superiority of the 4:2 compressor based partial product reduction technique as far as circuit delays, power consumption and architectural regularity are concerned.SPICE simulations of partial product generation using these schemes for an 8 bit multiplier suggest a worst case energy delay advantage of the order of 36% and 15% respectively for the 4:2 compressor based scheme in comparison with two different implementations of MBA.The corresponding figures for power reduction are of the order of 26% and 11% respectively.

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. Moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. Using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to SPICE LEVEL 3 has been achieved. The results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex CMOS circuits.>

The theory and implementation of a module generator for CMOS buffers are presented. The generator is written in the C language, and outputs optimal buffer designs in respect to a preselected objective function and layout. The user has the choice of minimizing delay, power, and area, or a combination of these, plus the choice of layout configuration. The research concentrates mainly on theoretical analysis, where variations of process, design, and layout parameters with respect to each objective function are studied in detail.>

A module generator for CMOS buffers have been written in C. The generator optimizes buffer design with respect to a user specified objective function both in terms of performance and layout.Speed, area, power consumption, power-delay, AT and AT" are selectively optimized before the layout is produced.Such layout is generated in various configurations depending on load size.Technology file is easily updatable.

An overview is presented of a micromanipulator vision system for use in automating various functions during the testing of a wafer for semiconducting parameters and inspection of VLSI circuits. Positioning the probe and touching a test pad are the chief concern of the work desired. A brief description of the experimental setup is given. The image processing techniques used in identifying and controlling the location of various components such as the probes and the test pads are discussed. The vision modules and an expert system using hierarchical plan generation to control the sequence of plans are included.>

An online control policy is presented using hierarchical control theory. It is shown that delays and stops are related to fuel consumption and exhaust emission rate. It is also shown that exhaust emission rate is related to fuel consumption in terms of the control variables cycle time, green time, and the relative offset. A general criterion is presented by which any of the functions of stops, delays, fuel consumption, or exhaust rate emission can be minimized. A complete mathematical description of the control system structure, software, and algorithms of control is given. The algorithms for the control parameters are given mathematically to cover the range of criterion function. All decision sets are evaluated and a procedure for the control policy is described. This online policy has the ability to adjust itself to suit the traffic variation in real time due to its prediction principle and also of selecting the desired function of minimization of stops, delays, fuel consumption, or exhaust emission rate for the whole network or subareas within the network.

An generalised approach for simulating relative offset of traffic signals in an urban traffic network is presented. It is shown that is is possible to optimize relative offset settings of signals for various criteria. A general criterion is proposed by which either delays, stops, fuel consumption, or carbon monoxide can be selected by a proper choice of constants. When these criteria are minimized, it was found that the best criterion to be selected for offset setting is the minimization of fuel consumption, since this in turn nearly minimizes the delays, stops, and carbon monoxide emission, and it has the effect of minimizing stops at low saturation and minimizing delays as the degree of saturation increases. Further analysis of the criterion function has shown that the functions minimized are uneven around their optimum offset value and in each case an early switching is favored. The expression to determine optimum offset is updated to calculated optimum offsets that minimizes fuel consumption or carbon monoxide emission.

The optimum split of a cycle time for a controlled traffic intersection within an urban network is determined for four objective functions. These are total delay, total number of stops, fuel consumption, and carbon monoxide minimization. It is shown that for each objective function, an optimum value of green split that minimizes the function exists. An expression for the optimum green is derived in each case. It is further shown that these optima do not coincide. A method of determining optimum green split based on a parameter defined as a flow factor is also introduced. This method is a function of the serviceability of the intersection with respect to minimizing total delay incurred by all vehicles at the intersection during one cycle.