Glioma is a type of brain tumor that causes mortality in many cases. Early diagnosis is an important factor. Typically, it is detected through MRI and then either a treatment is applied, or it is removed through surgery. Deep-learning techniques are becoming popular in medical applications and image-based diagnosis. Convolutional Neural Networks are the preferred architecture for object detection and classification in images. In this paper, we present a study to evaluate the efficiency of using CNNs for diagnosis aids in glioma detection and the improvement of the method when using a clustering method (Fuzzy C-means) for preprocessing the input MRI dataset. Results offered an accuracy improvement from 0.77 to 0.81 when using Fuzzy C-Means.

Deep Learning tools are widely used for medical image segmentation. The results produced by these techniques depend to a great extent on the data sets used to train the used network. Nowadays many cloud service providers offer the required resources to train networks and deploy deep learning networks. This makes the idea of segmentation as a cloud-based service attractive. In this paper we study the possibility of training, a generalized configurable, Keras U-Net to test the feasibility of training with images acquired, with specific instruments, to perform predictions on data from other instruments. We use, as our application example, the segmentation of Optic Disc and Cup which can be applied to glaucoma detection. We use two publicly available data sets (RIM-One V3 and DRISHTI) to train either independently or combining their data.

Falls are one of the most frequent causes of injuries in elderly people. Wearable Fall Detection Systems provided a ubiquitous tool for monitoring and alert when these events happen. Recurrent Neural Networks (RNN) are algorithms that demonstrates a great accuracy in some problems analyzing sequential inputs, such as temporal signal values. However, their computational complexity are an obstacle for the implementation in IoT devices. This work shows a performance analysis of a set of RNN architectures when trained with data obtained using different sampling frequencies. These architectures were trained to detect both fall and fall hazards by using accelerometers and were tested with 10-fold cross validation, using the F1-score metric. The results obtained show that sampling with a frequency of 25Hz does not affect the effectiveness, based on the F1-score, which implies a substantial increase in the performance in terms of computational cost. The architectures with two RNN layers and without a first dense layer had slightly better results than the smallest architectures. In future works, the best architectures obtained will be integrated in an IoT solution to determine the effectiveness empirically.

Neuromorphic engineers study models and implementations of systems that mimic neurons behavior in the brain. Neuro-inspired systems commonly use spikes to represent information. This representation has several advantages: its robustness to noise thanks to repetition, its continuous and analog information representation using digital pulses, its capacity of pre-processing during transmission time, ..., Furthermore, spikes is an efficient way, found by nature, to codify, transmit and process information. In this paper we propose, design, and analyze neuro-inspired building blocks that can perform spike-based analog filters used in signal processing. We present a VHDL implementation for FPGA. Presented building blocks take advantages of the spike rate coded representation to perform a massively parallel processing without complex hardware units, like floating point arithmetic units, or a large memory. Those low requirements of hardware allow the integration of a high number of blocks inside a FPGA, allowing to process fully in parallel several spikes coded signals.

This paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution.

Image convolution operations in digital computer systems are usually very expensive operations in terms of resource consumption (processor resources and processing time) for an efficient Real-Time application. In these scenarios the visual information is divided into frames and each one has to be completely processed before the next frame arrives in order to warranty the real-time. A spike-based philosophy for computing convolutions based on the neuro-inspired Address-Event-Representation (AER) is achieving high performances. In this paper we present two FPGA implementations of AER-based convolution processors for relatively small Xilinx FPGAs (Spartan-II 200 and Spartan-3 400), which process 64×64 images with 11×11 convolution kernels. The maximum equivalent operation rate that can be reached is 163.51 MOPS for 11×11 kernels, in a Xilinx Spartan 3 400 FPGA with a 50MHz clock. Formulations, hardware architecture, operation examples and performance comparison with frame-based convolution processors are presented and discussed.

Neuromorphic engineering tries to mimic biology in information processing. Address-event representation (AER) is a neuromorphic communication protocol for spiking neurons between different layers. AER bio-inspired image sensor are called ldquoretinardquo. This kind of sensors measure visual information not based on frames from real life and generates corresponding events. In this paper we provide an alternative, based on cheap FPGA, to this image sensors that takes images provided by an analog video source (video composite signal), digitalizes it and generates AER streams for testing purposes.

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies.

Address-Event-Representation (AER) is an \nasynchronous protocol for transferring the information of \nspiking neuro-inspired systems. Actually AER systems are able \nto see, to ear, to process information, and to learn. Regarding to \nthe actuation step, the AER has been used for implementing \nCentral Pattern Generator algorithms, but not for controlling \nthe actuators in a closed-loop spike-based way. In this paper we \nanalyze an AER based model for a real-time neuro-inspired \nclosed-loop control system. We demonstrate it into a differential \ncontrol system for a two-wheel vehicle using feedback AER \ninformation. PFM modulation has been used to power the DC \nmotors of the vehicle and translation into AER of encoder \ninformation is also presented for the close-loop. A codesign \nplatform (called AER-Robot), based into a Xilinx Spartan 3 \nFPGA and an 8051 USB microcontroller, with power stages for \nfour DC motors has been used for the demonstrator.

In this demo we propose a method for computing real time convolution on AER images. For that we use signed events. The AER events produced on an AER retina or an image/video to AER conversor, are processed using a probabilistic multi event mapper that produces more than one event for each incoming event according to an assigned probability. Kernel convolution size are limited by mapping tables size (on board RAM) and AER bus bandwidth. On reconstruction signed events needs to be simplified (subtracted) to get final convolved image. For that two different methods are proposed.

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16$\,\times\,$16 has been implemented with programmable kernel size of up to 16$\, \times\,$16. The chip has been fabricated in a standard 0.35-${\mu }$m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down tonanoamperesor evenpicoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we pro

This paper describes a high-speed USB2.0 address-event representation (AER) interface that allows simultaneous monitoring and sequencing of precisely timed AER data. This low-cost (<$100), two chip, bus powered interface can achieve sustained AER event rates of 5 megaevents per second (Meps). Several boards can be electrically synchronized, allowing simultaneous synchronized capture from multiple devices. It has three parallel AER ports, one for sequencing, one for monitoring and one for passing through the monitored events. This paper also describes the host software infrastructure that makes the board usable for a heterogeneous mixture of AER devices and that allows recording and playback of recorded data.

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.

In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured cortical-like layers for sophisticated processing. The paper includes a few examples that have demonstrated the potential of this technology for high-speed vision processing, such as a multilayer event processing network of 5 sequential cortical-like layers, and a recognition system capable of discriminating propellers of different shape rotating at 5000 revolutions per second (300000 revolutions per minute).

Address-event-representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them in real time, while performing some processing. To develop and test AER based systems it is convenient to have a set of instruments that would allow to: generate AER streams, monitor the output produced by neural chips and modify the spike stream produced by an emitting chip to adapt it to the requirements of the receiving elements. In this paper we present a set of tools that implement these functions developed in the CAVIAR EU project

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). To develop AER based systems for image processing it is very convenient to have available some kind of tool for generating AER streams from on-computer stored images. In this paper we present a hardware method for generating AER streams with Poisson statistics in real time from a sequence of images stored in a computer's memory. We quantify that the events generated follow a Poisson distribution using the Kolmogorov-Smirnov test. We have developed a USB-AER board, based on the Xilinx Spartan II FPGA and the Cygnal 8051 microcontroller, developed by our RTCAR group have been used for the analysis

Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows: (a) to read AER interchip traffic; and (b) inject a sequence of events to the AER structure. This paper presents a PCI to AER interface, that dispatches a sequence of events with timing information. It is able to recovery the possible delays introduced by AER bus. It has been implemented in real time hardware using VHDL and tested in a PCI-AER board, developed by authors, that currently capable to send and receive events at a peak rate of 16 Mev/sec, and a typical rate of 10 Mev/sec

This paper addresses the problem of converting a conventional video stream based on sequences of frames into the spike event-based representation known as the address-event-representation (AER). In this paper we concentrate on rate-coded AER. The problem is addressed as an algorithmic problem, in which different methods are proposed, implemented and tested through software algorithms. The proposed algorithms are comparatively evaluated according to different criteria. Emphasis is put on the potential of such algorithms for a) doing the frame-based to event-based representation in real time, and b) that the resulting event streams ressemble as much as possible those generated naturally by rate-coded address-event VLSI chips, such as silicon AER retinae. It is found that simple and straightforward algorithms tend to have high potential for real time but produce event distributions that differ considerably from those obtained in AER VLSI chips. On the other hand, sophisticated algorithms that yield better event distributions are not efficient for real time operations. The methods based on linear-feedback-shift-register (LFSR) pseudorandom number generation is a good compromise, which is feasible for real time and yield reasonably well distributed events in time. Our software experiments, on a 1.6-GHz Pentium IV, show that at 50% AER bus load the proposed algorithms require between 0.011 and 1.14 ms per 8 bit-pixel per frame. One of the proposed LFSR methods is implemented in real time hardware using a prototyping board that includes a VirtexE 300 FPGA. The demonstration hardware is capable of transforming frames of 64 x 64 pixels of 8-bit depth at a frame rate of 25 frames per second, producing spike events at a peak rate of 10(7) events per second.

A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-event- representation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.

We present an analytical model for single-slave Bluetooth piconets when the coexistence of multiple interfering devices produces collisions. Closed-form expressions for the channel throughput and the mean packet delay are obtained, including the time spent waiting on the node's queue. The effect of propagation losses and asynchronous piconets are also discussed. The results of the analysis are validated through simulation.

Address-event-representation (AER) is a communication protocol that emulates the nervous system's neurons communication, and that is typically used for transferring images between chips. It was originally developed for bio-inspired and real-time image processing systems. Such systems may consist of a complicated hierarchical structure with many chips that transmit images among them in real time, while performing some processing. In this paper several software methods for generating AER streams from images stored in a computer's memory are presented. A hardware version that works in real-time is also being studied. All of them have been evaluated and compared.

Several authors have proposed some methods for applying path following in specific cases to mobile robots. When we try to extend the path following approach to the general problem several difficulties arise. We present a generalized technique to apply path following to a mobile robot with nonholonomic constraints. As an application example, we expose the case of mobile robots with a higher degree of manoeuvrability than the typical car-like robots. In particular we consider a robot that can turn around itself making a zero-radius turn; a case still not resolved as far as we know. Finally we propose a suitable control law for this example that ensures asymptotical convergence.