Demo Data from SIGIR 2026 / reviewers in the wild / expert
T. C. Hu
dblp:h/TCHu
· DBLP profile ↗
29ranked-venue papers
12as first author
0since 2021 · last 2018
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 14 · 2 first-authorTheory of computation · 12 · 8 first-authorComputer networks · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
8 papers |
Electronic design automation · 82% Parallel and multicore computing · 10% Distributed systems · 8% | |
| Theoretical computer science
7 papers |
Algorithms and data structures · 58% Mathematical optimization · 25% Graph algorithms and graph theory · 11% | |
| Artificial intelligence
1 paper |
Motion planning and robot control · 50% Robot navigation and mapping · 50% |
Topics — the 30 heaviest of 31, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.1 | 5 | 1995 | A replication cut for two-way partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Prim-Dijkstra tradeoffs for improved performance-driven routing tree design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 Performance-Driven Partitioning Using a Replication Graph Approach · DAC 1995 |
Electronic design automation › physical design
circuit partitioning |
0.0 | 1 | 1995 | Performance-Driven Partitioning Using a Replication Graph Approach · DAC 1995 |
Parallel and multicore computing
graph partitioning |
0.0 | 1 | 1995 | A replication cut for two-way partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Distributed systems
replication |
0.0 | 1 | 1995 | Performance-Driven Partitioning Using a Replication Graph Approach · DAC 1995 |
Electronic design automation › physical design › routing
timing-driven routing |
0.0 | 1 | 1995 | Prim-Dijkstra tradeoffs for improved performance-driven routing tree design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1994 | A multi-probe approach for MCM substrate testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1994 | A multi-probe approach for MCM substrate testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1994 | A multi-probe approach for MCM substrate testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Robotics › Motion planning and robot control
motion planning |
0.0 | 1 | 1993 | Optimal robust path planning in general environments · IEEE Trans. Robotics Autom. 1993 |
Robotics › Robot navigation and mapping › mobile robot navigation › navigation planning
robust path planning |
0.0 | 1 | 1993 | Optimal robust path planning in general environments · IEEE Trans. Robotics Autom. 1993 |
Algorithms and data structures
dynamic programming |
0.0 | 3 | 1984 | Computation of Matrix Chain Products. Part II · SIAM J. Comput. 1984 Computation of Matrix Chain Products. Part I · SIAM J. Comput. 1982 Some Theorems about Matrix Multiplication (Extended Abstract) · FOCS 1980 |
Algorithms and data structures › dynamic programming
matrix chain multiplication |
0.0 | 3 | 1984 | Computation of Matrix Chain Products. Part II · SIAM J. Comput. 1984 Computation of Matrix Chain Products. Part I · SIAM J. Comput. 1982 Some Theorems about Matrix Multiplication (Extended Abstract) · FOCS 1980 |
Mathematical optimization › combinatorial optimization
optimal parenthesization |
0.0 | 3 | 1984 | Computation of Matrix Chain Products. Part II · SIAM J. Comput. 1984 Computation of Matrix Chain Products. Part I · SIAM J. Comput. 1982 Some Theorems about Matrix Multiplication (Extended Abstract) · FOCS 1980 |
Electronic design automation
logic synthesis |
0.0 | 2 | 1985 | A heuristic algorithm for PLA block folding · DAC 1985 Optimum reduction of programmable logic array · DAC 1983 |
Mathematical optimization
combinatorial optimization |
0.0 | 2 | 1984 | Computation of Matrix Chain Products. Part II · SIAM J. Comput. 1984 Computation of Matrix Chain Products. Part I · SIAM J. Comput. 1982 |
Algorithms and data structures › search algorithms
binary search |
0.0 | 1 | 1987 | Binary Search on a Tape · SIAM J. Comput. 1987 |
Algorithms and data structures › data structure design › search structures
search trees |
0.0 | 1 | 1987 | Binary Search on a Tape · SIAM J. Comput. 1987 |
Algorithms and data structures › search algorithms
sequential search |
0.0 | 1 | 1987 | Binary Search on a Tape · SIAM J. Comput. 1987 |
Electronic design automation › logic synthesis › technology mapping
FPGA technology mapping |
0.0 | 1 | 1995 | A replication cut for two-way partitioning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995 |
Electronic design automation › logic synthesis › logic optimization
PLA folding |
0.0 | 1 | 1985 | A heuristic algorithm for PLA block folding · DAC 1985 |
Electronic design automation › logic synthesis › programmable logic array
PLA optimization |
0.0 | 1 | 1983 | Optimum reduction of programmable logic array · DAC 1983 |
Graph algorithms and graph theory
graph decomposition |
0.0 | 1 | 1991 | The Orientation of Modules Based on Graph Decomposition · IEEE Trans. Computers 1991 |
Graph algorithms and graph theory
minimum cut |
0.0 | 1 | 1991 | The Orientation of Modules Based on Graph Decomposition · IEEE Trans. Computers 1991 |
Parallel and multicore computing
task allocation |
0.0 | 1 | 1979 | Assignment of Task in a Distributed Processor System with Limited Memory · IEEE Trans. Computers 1979 |
Parallel and multicore computing
task scheduling |
0.0 | 1 | 1979 | Assignment of Task in a Distributed Processor System with Limited Memory · IEEE Trans. Computers 1979 |
Algorithms and data structures › combinatorial algorithms › enumeration algorithms
binary tree generation |
0.0 | 1 | 1977 | Generating Binary Trees Lexicographically · SIAM J. Comput. 1977 |
Combinatorics and discrete mathematics › enumeration
combinatorial generation |
0.0 | 1 | 1977 | Generating Binary Trees Lexicographically · SIAM J. Comput. 1977 |
Distributed computing theory › distributed graph algorithms
minimum-weight spanning tree |
0.0 | 1 | 1974 | Optimum Communication Spanning Trees · SIAM J. Comput. 1974 |
Approximation and online algorithms › approximation algorithms
network design |
0.0 | 1 | 1974 | Optimum Communication Spanning Trees · SIAM J. Comput. 1974 |
Approximation and online algorithms › approximation algorithms › network design
optimum communication spanning tree |
0.0 | 1 | 1974 | Optimum Communication Spanning Trees · SIAM J. Comput. 1974 |
Methods — techniques the papers use, named apart from their topics
graph decomposition · 0.0NP-completeness proof · 0.0replication graph · 0.0prim algorithm · 0.0fiduccia-mattheyses algorithm · 0.0elmore delay analysis · 0.0dijkstra algorithm · 0.0traveling salesman problem · 0.0routing tree model · 0.0network flow · 0.0graph search · 0.0dynamic programming · 0.0decision tree analysis · 0.0column intersection graph · 0.0combinatorial optimization · 0.0unranking · 0.0lexicographic ranking · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Theory and Algorithms of Physical DesignabstractNo abstract available. Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng |
ISPD | 2 |
| 2005 | Optimal Integer Alphabetic Trees in Linear Time
T. C. Hu, Lawrence L. Larmore, J. David Morgenthaler |
ESA | 1 |
| 1997 | Physical design: mathematical models and methodsabstractThe title of t,his talk is too broad to be covered in one day nnd I realize that there are many experts of different backgrounds, 'as well as students, in the audience.Thus, I have selected a fern basic concepts and two numerical examples to supplement my slides. T. C. Hu |
ISPD | 1 |
| 1995 | Performance-Driven Partitioning Using a Replication Graph Approach
Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu |
DAC | 4 |
| 1995 | Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting MethodsabstractStochastic hill-climbing algorithms, particularly simulated annealing (SA) and threshold acceptance (TA), have become very popular for global optimization applications. Typical implementations of SA or TA use monotone temperature or threshold schedules, and are not formulated to accommodate practical time limits. We present a new threshold acceptance strategy called Old Bachelor Acceptance (OBA), which has three distinguishing features: (i) it is specifically motivated by the practical requirement of optimization within a prescribed time bound, (ii) the threshold schedule is self-tuning, and (iii) the threshold schedule is non-monotone, with threshold values even allowed to become negative. The standard implementation of the TA method of Dueck and Scheuer is a special case of OBA. Experiments using several classes of symmetric traveling salesman problem instances show that OBA can outperform previous hill-climbing methods for time-critical optimizations. A number of directions for future work are suggested. INFORMS Journal on Computing, ISSN 1091-9856, was published as ORSA Journal on Computing from 1989 to 1995 under ISSN 0899-1499. T. C. Hu, Andrew B. Kahng, Chung-Wen Albert Tsao |
INFORMS J. Comput. | 1 |
| 1995 | Prim-Dijkstra tradeoffs for improved performance-driven routing tree designabstractAnalysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimal algorithms due to Prim (1957) and Dijkstra (1959). Previous "shallow-light" techniques are both less direct and less effective: in practice, our methods achieve uniformly superior cost-radius tradeoffs. Timing simulations for a range of IC and MCM interconnect technologies show that our wirelength savings yield reduced signal delays when compared to shallow-light or standard minimum spanning tree and Steiner tree routing.> Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1995 | A replication cut for two-way partitioningabstractGraph partitioning is crucial in multiple-chip design, floorplanning and mapping large logic networks into multiple FPGA's. Replication logic can be used to improve the partitioning. Given a network G with only two-pin nets and a pair of nodes s and t to be separated, we introduce a replication graph and an O(mn log(n/sup 2//m)) algorithm for optimum partitioning with replication and without size constraints, where m and n denote the number of nets and the number of nodes in G, respectively. In VLSI designs, each partition has size constraints and the given network contains multiple-pin nets. A heuristic extension is adopted to construct replication graphs with multiple-pin nets. Then we use a directed Fiduccia-Mattheyses algorithm in the constructed replication graph to solve the replication cut problem with size constraints.> Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 1994 | A multi-probe approach for MCM substrate testingabstractMulti-chip module (MCM) technology has become an important means to package high performance systems. An important task during the packaging process is to check for possible open, short, and high resistance faults in the wiring networks of the bare MCM substrates, which is called substrate testing. After examining several substrate testing methodologies, we find that multi-probe or k-probe testers are cost-effective for substrate testing. However, the testing speed of this method is not high; hence, we focus on improving the throughput by reducing the number of tests and by deriving good probe routes. For test size reduction, we propose a routing tree model to capture the wiring structure of a given net; then by taking advantage of the routing tree, we generate a minimum number of tests while ensuring complete open fault coverage. Our algorithm reduces the number of tests by up to 50% compared to that of previous approaches. Given a routing tree with its node degree bounded by a constant, our test generation algorithm runs in linear time with respect to the number of leaves of the tree. For probe route scheduling, we observe that in order to obtain a balanced and efficient scheduling, the routes of different probes must be considered simultaneously, which motivates our Multi-Dimensional Traveling Salesman Problem (MDTSP) formulation. Our package has been installed on existing substrate testers and has achieved encouraging results.> So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 1994 | Block-oriented programmable design with switching network interconnectabstractA block-oriented programmable design with switching network interconnect is proposed for fast turn-around, low manufacturing cost, and layout-independent high-speed systems. We introduce the architecture and investigate the constraints and properties originated from the architecture. We show that routability is the most crucial concern for a successful design, and propose objective functions as well as algorithms for switching network optimization. The mapping for the circuits is performed by partitioning, placement, and routing using a maximum matching method. The integration of the whole system demonstrates excellent results in terms of circuit usage.> Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, M. Liddel |
IEEE Trans. Very Large Scale Integr. Syst. | 4 |
| 1993 | A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing
Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng |
ISCAS | 2 |
| 1993 | Optimal robust path planning in general environmentsabstractWe address robust path planning for a mobile agent in a general environment by finding minimum cost source-destination paths having prescribed widths. The main result is a new approach that optimally solves the robust path planning problem using an efficient network flow formulation. Our algorithm represents a significant departure from conventional shortest-path or graph search based methods; it not only handles environments with solid polygonal obstacles, but also generalizes to arbitrary cost maps that may arise in modeling incomplete or uncertain knowledge of the environment. Simple extensions allow us to address higher dimensional problem instances and minimum-surface computations; the latter is a result of independent interest. We use an efficient implementation to exhibit optimal path-planning solutions for a variety of test problems. The paper concludes with open issues and directions for future work.> T. C. Hu, Andrew B. Kahng, Gabriel Robins |
IEEE Trans. Robotics Autom. | 1 |
| 1992 | An optimal probe testing algorithm for the connectivity verification of MCM substratesabstractThe k-probe testing methodology is an effective approach to detect open and short faults in MCM substrates. An algorithm which generates the minimum number of tests for complete open fault coverage is proposed. For k equals two, the algorithm is able to reduce the test size by up to 50% compared with that generated by an ordinary approach. A multidimensional traveling salesman problem formulation is developed to optimize probe routes. The approach has been tested on substrate testers and has achieved excellent results.> So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu |
ICCAD | 4 |
| 1992 | Maximum Concurrent Flows and Minimum Cuts
Chung-Kuan Cheng, T. C. Hu |
Algorithmica | 2 |
| 1991 | The Orientation of Modules Based on Graph DecompositionabstractIn the layout stage of VLSI and printed circuit board (PCB) design, after all circuit modules (rectangular) are placed, it is possible to flip the modules so as to reduce the total net length. The authors formulate the orientation of modules as a graph problem and prove it to be NP-complete. The orientation problem is shown to be equivalent to finding a minimum cut of a graph with some arcs of negative capacities. In many cases, the graph can be decomposed into subgraphs to reduce the search space for optimum orientation. Experiments with real cases show that module orientation reduces the total net length and improves the routability.> Chung-Kuan Cheng, So-Zen Yao, T. C. Hu |
IEEE Trans. Computers | 3 |
| 1990 | Ancestor Tree for Arbitrary Multi-Terminal Cut Functions
Chung-Kuan Cheng, T. C. Hu |
IPCO | 2 |
| 1987 | An effective algorithm for optimal PLA column folding
Yue-Sun Kuo, T. C. Hu |
Integr. | 2 |
| 1987 | Graph folding and programmable logic arrayabstractAbstract The problem of compacting a programmable logic array is formulated as the following graph problem. Given a red‐edge bipartite graph, how to add maximum number of independent green edges such that there are no cycles formed by alternating red and green edges. For this NP‐complete problem, we present a polynomial heuristic algorithm which gives an optimum solution when the red bipartite graph satisfies certain conditions, e.g., a tree. When the bipartite graph does not satisfy these conditions, the heuristic algorithm gives a solution with worst‐case error bound. For a red bipartite graph with given cardinality, we give a tight upper bound on the number of green edges. T. C. Hu, Yue-Sun Kuo |
Networks | 1 |
| 1987 | Binary Search on a TapeabstractGiven n records stored alphabetically on a tape, any comparison search procedure can be characterized by a binary tree. The complete binary tree (binary search) uses the minimum number of comparisons but not the minimum number of movements. The linear binary tree (sequential search) uses the minimum number of movements but not the minimum number of comparisons. A tape-optimal tree is a tree which minimizes the total cost of comparisons and movements. The tape-optimal tree is a “hybrid” of the linear tree and the complete binary tree, and is characterized for arbitrary n. T. C. Hu, Michelle L. Wachs |
SIAM J. Comput. | 1 |
| 1986 | A decomposition algorithm for multi-terminal networks flows
Man-tak Shing, T. C. Hu |
Discret. Appl. Math. | 2 |
| 1985 | A heuristic algorithm for PLA block foldingabstractThe folding of programmable logic array (PLA) is considered. We develop a heuristic algorithm for optimal block folding. The algorithm is based on the column intersection graph associated with the PLA. Then the techniques of graph partitioning and two-objective linear programming are applied. Test results will be demonstrated to show the effectiveness of the algorithm. Yue-Sun Kuo, T. C. Hu |
DAC | 3 |
| 1984 | Computation of Matrix Chain Products. Part IIabstractThis paper considers the computation of matrix chain products of the form $M_1 \times M_2 \times \cdots \times M_{n - 1} $. If the matrices are of different dimensions, the order in which the matrices are computed affects the number of operations. An optimum order is an order which minimizes the total number of operations. Some theorems about an optimum order of computing the matrices have been presented in Part I [SIAM J. Comput., 11 (1982), pp. 362–373]. Based on those theorems, an $O(n\log n)$ algorithm for finding the optimum order is presented here. T. C. Hu, Man-tak Shing |
SIAM J. Comput. | 1 |
| 1983 | Optimum reduction of programmable logic array
T. C. Hu, Yue-Sun Kuo |
DAC | 1 |
| 1982 | Computation of Matrix Chain Products. Part IabstractThis paper considers the computation of matrix chain products of the form $M_1 \times M_2 \times \cdots \times M_{n - 1} $. If the matrices are of different dimensions, the order in which the product is computed affects the number of operations. An optimum order is an order which minimizes the total number of operations. We present some theorems about an optimum order of computing the matrices. Based on these theorems, an $O(n\log n)$ algorithm for finding an optimum order will be presented in Part II. T. C. Hu, Man-tak Shing |
SIAM J. Comput. | 1 |
| 1980 | Some Theorems about Matrix Multiplication (Extended Abstract)abstractThis paper considers the computation of matrix chain products of the form M1 × M2 ×...× Mn-1. If the matrices are of different dimensions, the order in which the matrices are computed affects the number of operations. An optimum order is an order which minimizes the total number of operations. We present some theorems about an optimum order of computing the matrices. Based on these theorems, an O(n log n) algorithm for finding the optimum order is presented. T. C. Hu, Man-tak Shing |
FOCS | 1 |
| 1979 | Assignment of Task in a Distributed Processor System with Limited MemoryabstractA recently published algorithm shows how to assign modules to a two-processor computer system with distributed execution so as to minimize the total of execution costs and interprocessor communication costs. In this paper we consider the same problem except that one processor has limited memory capacity. Although this problem is NP-complete, techniques based on the Gomory–Hu tree from network flow theory can be applied to instances of the problem to obtain a reduction in complexity. A new technique based on a graph called the inclusive cut graph is shown to be an even more powerful tool. These two techniques can solve some instances of the problem completely; still others are reduced sufficiently to be susceptible to enumerative techniques. In the worst case, the techniques yield no reduction in problem size. Gururaj S. Rao, Harold S. Stone, T. C. Hu |
IEEE Trans. Computers | 3 |
| 1977 | Tree decomposition algorithm for large networksabstractAbstract Decomposition algorithms have been proposed for finding the shortest paths between all pairs of nodes in a large network. The central idea is to treat the large network as several small networks overlapping each other. When the small networks overlap each other linearly, algorithms have been proposed to treat each small network individually. The present note treats the case of small networks overlapping each other like a tree. W. J. Blewett, T. C. Hu |
Networks | 2 |
| 1977 | Generating Binary Trees LexicographicallyabstractWe represent a binary tree by the level numbers of its leaves from left to right. Thus every binary tree of n leaves corresponds to a sequence of n numbers. We first give the necessary and sufficient conditions for a sequence to represent a binary tree; then we give an algorithm for generating all the feasible sequences lexicographically as a list. Also, algorithms are developed to determine the position of a given sequence, or to generate the sequence of a given position. Finally, it is shown that the average time per sequence generated is constant (independent of the length of the sequence). Frank Ruskey, T. C. Hu |
SIAM J. Comput. | 2 |
| 1974 | Optimum Communication Spanning TreesabstractGiven a set of nodes $N_i (i = 1,2, \cdots ,n)$ which may represent cities and a set of requirements $r_{ij} $ which may represent the number of telephone calls between $N_i $ and $N_j $, the problem is to build a spanning tree connecting these n nodes such that the total cost of communication of the spanning tree is a minimum among all spanning trees. The cost of communication for a pair of nodes is $r_{ij} $ multiplied by the sum of the distances of arcs which form the unique path connecting $N_i $ and $N_j $ in the spanning tree. Summing over all $\begin{pmatrix} n \\ 2 \ \end{pmatrix}$ pairs of nodes, we have the total cost of communication of the spanning tree. Note that the problem is different from the minimum spanning tree problem solved by Kruskal and Prim. T. C. Hu |
SIAM J. Comput. | 1 |
| 1972 | Least Upper Bound on the Cost of Optimum Binary Search Trees
T. C. Hu, Kay Chen Tan |
Acta Informatica | 1 |