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Rafael H. Saavedra

dblp:s/RafaelHSaavedra · also Rafael H. Saavedra-Barrera · DBLP profile ↗
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9ranked-venue papers
7as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 6 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Performance modeling and evaluation · 64% Memory systems · 28% Processor architecture and microarchitecture · 6%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 13 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
benchmarking
0.051996
Analysis of Benchmark Characteristics and Benchmark Performance Prediction · ACM Trans. Comput. Syst. 1996
Micro benchmark analysis of the KSR1 · SC 1993
Machine Characterization Based on an Abstract High-Level Language Machine · IEEE Trans. Computers 1989
Performance modeling and evaluation
workload characterization
0.031996
Analysis of Benchmark Characteristics and Benchmark Performance Prediction · ACM Trans. Comput. Syst. 1996
Performance Characterization of Optimizing Compilers · IEEE Trans. Software Eng. 1995
Machine Characterization Based on an Abstract High-Level Language Machine · IEEE Trans. Computers 1989
Memory systems
cache
0.021995
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes · IEEE Trans. Computers 1995
Micro benchmark analysis of the KSR1 · SC 1993
Performance modeling and evaluation › performance prediction
execution time prediction
0.021996
Analysis of Benchmark Characteristics and Benchmark Performance Prediction · ACM Trans. Comput. Syst. 1996
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes · IEEE Trans. Computers 1995
Performance modeling and evaluation › benchmarking › benchmark suite analysis
benchmark characterization
0.011996
Analysis of Benchmark Characteristics and Benchmark Performance Prediction · ACM Trans. Comput. Syst. 1996
Performance modeling and evaluation
performance prediction
0.011996
Analysis of Benchmark Characteristics and Benchmark Performance Prediction · ACM Trans. Comput. Syst. 1996
Processor architecture and microarchitecture
abstract machine
0.011995
Performance Characterization of Optimizing Compilers · IEEE Trans. Software Eng. 1995
Memory systems › cache
cache behavior
0.011995
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes · IEEE Trans. Computers 1995
Memory systems › virtual memory management
TLB performance
0.011995
Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes · IEEE Trans. Computers 1995
Performance modeling and evaluation › benchmarking
microbenchmarking
0.011993
Micro benchmark analysis of the KSR1 · SC 1993
Memory systems
shared memory
0.011993
Micro benchmark analysis of the KSR1 · SC 1993
Interconnection networks and networks-on-chip
ring network
0.011993
Micro benchmark analysis of the KSR1 · SC 1993
Performance modeling and evaluation
simulation
0.011989
Machine Characterization Based on an Abstract High-Level Language Machine · IEEE Trans. Computers 1989

Methods — techniques the papers use, named apart from their topics

performance characterization · 0.0machine-independent model of program execution · 0.0miss ratio analysis · 0.0cache and TLB measurement · 0.0microbenchmarks · 0.0pershape analysis · 0.0performance measurement · 0.0
YearPublicationVenuePosition
2001 Adaptive software prefetching in scalable multiprocessors using cache information
Daeyeon Park, Byeong Hag Seong, Rafael H. Saavedra
Parallel Comput.3
1996 The Limits and Effectiveness of Data Prefetching on Scalable Multiprocessors
Weihua Mao, Rafael H. Saavedra
Perform. Evaluation2
1996 Analysis of Benchmark Characteristics and Benchmark Performance Prediction
abstract
Standard benchmarking provides to run-times for given programs on given machines, but fails to provide insight as to why those results were obtained (either in terms of machine or program characteristics) and fails to provide run-times for that program on some other machine, or some other programs on that machine. We have developed a machine-imdependent model of program execution to characterize both machine performance and program execution. By merging these machine and program characterizations, we can estimate execution time for arbitrary machine/program combinations. Our technique allows us to identify those operations, either on the machine or in the programs, which dominate the benchmark results. This information helps designers in improving the performance of future machines and users in tuning their applications to better utilize the performance of existing machines. Here we apply our methodology to characterize benchmarks and predict their execution times. We present extensive run-time statistics for a large set of benchmarks including the SPEC and Perfect Club suites. We show how these statistics can be used to identify important shortcoming in the programs. In addition, we give execution time estimates for a large sample of programs and machines and compare these against benchmark results. Finally, we develop a metric for program similarity that makes it possible to classify benchmarks with respect to a large set of characteristics.
Rafael H. Saavedra, Alan Jay Smith
ACM Trans. Comput. Syst.1
1995 Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes
abstract
In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (1) developing a high level program to measure the design and performance of the cache and TLB units; (2) using those measurements, along with published miss ratio data, to improve the accuracy of our runtime predictions; (3) using our analysis tools and measurements to study and compare the design of several machines, with particular reference to their cache and TLB performance. As part of this work, we describe the design and performance of the cache and TLB for ten machines. The work presented, in this paper extends a powerful technique for the evaluation and analysis of both computer systems and their workloads; this methodology is valuable both to computer users and computer system designers.>
Rafael H. Saavedra, Alan Jay Smith
IEEE Trans. Computers1
1995 Performance Characterization of Optimizing Compilers
abstract
Optimizing compilers have become an essential component in achieving high levels of performance. Various simple and sophisticated optimizations are implemented at different stages of compilation to yield significant improvements, but little work has been done in characterizing the effectiveness of optimizers, or in understanding where most of this improvement comes from. We study the performance impact of optimization in the context of our methodology for CPU performance characterization based on the abstract machine model. The model considers all machines to be different implementations of the same high level language abstract machine; in previous research, the model has been used as a basis to analyze machine and benchmark performance. We show that our model can be extended to characterize the performance improvement provided by optimizers and to predict the run time of optimized programs, and measure the effectiveness of several compilers in implementing different optimization techniques.>
Rafael H. Saavedra, Alan Jay Smith
IEEE Trans. Software Eng.1
1994 Performance and Optimization of Data Prefetching Strategies in Scalable Multiprocessors
Rafael H. Saavedra, Weihua Mao, Kai Hwang 0001
J. Parallel Distributed Comput.1
1993 Micro benchmark analysis of the KSR1
abstract
A new approach, micro benchmarks, has recently been developed. Using this technique, we have analyzed the KSR1, and in particular the "ALLCACHE" memory architecture and ring interconnection. We have been able to elucidate many facets of memory performance. The technique has enabled us to identify and characterize parts of the memory design not described by Kendall Square Research. Our results show that a miss in the local cache can incur a penalty ranging from 7.5 microseconds to 500 microseconds (when a dirty "page" in the local cache must be evicted). The programmer must be very careful in placement and accessing of data to obtain maximum performance from the KSR1; the data presented here will help in understanding the performance actually obtained. 1. Introduction The KSR1 from Kendall Square Research is a novel new parallel computer. It is the first commercial machine embodying a scalable all cache form of shared memory architecture. In addition, there are a number of other inter...
Rafael H. Saavedra, R. Stockton Gaines, Michael J. Carlton
SC1
1990 Analysis of Multithreaded Architectures for Parallel Computing
abstract
Multithreading has been proposed as an architectural strategy for tolerating latency in multiprocessors and, through limited empirical studies, shown to offer promise.This paper develops an analytical model of multithreaded processor behavior based on a small set of architectural and program parameters.The model gives rise to a large Markov chain, which is solved to obtain a formula for processor efficiency in terms of the number of threads per processor, the remote reference rate, the latency, and the cost of switching between threads.It is shown that a multithreaded processor exhibits three operating regimes: linear (efficiency is proportional to the number of threads), transition, and saturation (efficiency depends only on the remote reference rate and switch cost).Formulae for regime boundaries are derived.The model is embellished to reflect cache degradation due to multithreading, using an analytical model of cache behavior, demonstrating that retums diminish as the number threads becomes large.predictions from the embellished model correlate well with published empirical measurements.prescriptive use of the model under various scenarios indicates that multithreading is effective, but the Ilumber of useful threads per processor is fairly small.
Rafael H. Saavedra, David E. Culler, Thorsten von Eicken
SPAA1
1989 Machine Characterization Based on an Abstract High-Level Language Machine
abstract
Measurements are presented for a large number of machines ranging from small workstations to supercomputers. The authors combine these measurements into groups of parameters which relate to specific aspects of the machine implementation, and use these groups to provide overall machine characterizations. The authors also define the concept of pershapes, which represent the level of performance of a machine for different types of computation. A metric based on pershapes is introduced that provides a quantitative way of measuring how similar two machines are in terms of their performance distributions. The metric is related to the extent to which pairs of machines have varying relative performance levels depending on which benchmark is used.>
Rafael H. Saavedra, Alan Jay Smith, Eugene N. Miya
IEEE Trans. Computers1