A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/√Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

This paper presents a novel receiving scheme with combining phase error tracker (PET) and MMSE equalizer for multi-band ultra wideband (MB-UWB). A low complexity phase error tracker is developed to track the phase error caused by carrier frequency offset (CFO) and sampling clock offset (SCO), which will cause fatal error in coherent OFDM demodulation. The proposed joint scheme makes the receiver more robust to CFO and SCO effects and can suppresses the error rate at low SNR and high data rate receiving. With through MB-UWB simulation, the proposed scheme contributes 1.36~7.25 dB gain in SNR for 8% packet error rate (PER) specification in different transmission modes. Furthermore, the low complexity algorithm can benefit the low area and low power design for wireless applications.

A CMOS distributed amplifier with current reuse optimization is presented. Using current reuse technique, the distributed amplifier achieves low power consumption while retaining the same gain-bandwidth product in comparison with standard common-source topology. The DA demonstrates low current consumption of only 12.9 mA with 4 dB gain from 3 to 8 GHz using a 0.18-/spl mu/m CMOS technology. An analog behavior model is also developed for system-level simulation to shorten the design time and increase design quality for future integrated wide-band transceivers.

A novel pseudo noise code acquisition combined with the newly proposed adaptive sampling rate and threshold control (ASTC) algorithm is derived for low-power spread-spectrum systems with complementary metal-oxide-semiconductor implementations. Low-power performance can be achieved by reducing the sampling rate of the proposed system while maintaining the system performance. The sampling rate is dynamically updated due to the change of the channel noise level. Under the assumptions that the channel is additive white Gaussian noise slow-fading channel, up to 74.3% reduction in power consumption compared to the conventional fixed-sampling rate and fixed-threshold architecture is demonstrated with insignificant increase of system complexity. The proposed architecture can be applied to the design of low-power and controllable-performance spread-spectrum communication systems.

A low complexity 3-stage parallel interference cancellation (LCPIC) receiver for DS-CDMA cellular systems is proposed and analyzed. Based on numerical analyses, the power efficiency of the LCPIC receiver is close to that of the 3-stage PIC receiver and better than that of the 2-stage PIC receiver in AWGN with either perfect power control or log-normal power control error. In addition, the near-far resistance of the LCPIC, 2-stage, 3-stage PIC, and SIC receivers are analogous since their performances are undistinguishable in near-far channels. Still more, the computational complexity, which is in terms of the needs of flops per bit decision, of the LCPIC receiver is much less than that of the 3-stage PIC receiver and only a little more than that of the 2-stage PIC receiver.

A programmable pipelined digital differential matched filter (PDMF) implemented for a direct sequence spread spectrum receiver is proposed in this paper. To reduce the power consumption, the PDMF architecture is based on the synchronization combined PN code phase acquisition algorithm. Compared with the conventional PN code phase acquisition algorithm, the theoretical analysis result indicates that the PDMF acquires both power efficient and preferable detection. Depending on different applications, programmability allows the PDMF to implement 3-tap, 5-tap, or 11-tap Barker codes with the same hardware but different precisions for each tap coefficient. For short tap Baker codes, the architecture could adopt more precision on each tap coefficient to resist the channel noise. Simulation results also show that there are fewer errors of high sample precision with the same tape.

In this paper, we use Spatial/Temporal decimation on 3DPAC for very-low-bit-rate video transmission. After combing the decimation in space and time domain, it is also proved that 3DPAC is effective and suitable in very low bit rate application in the environment with limited bandwidth. Wiener interpolator and linear interpolator are applied for quality enhancement. The visual quality can be retained under low bit rate. With the aid of codebook design to gain more compression, 3DPAC would be support the applications with bit rate lower than 40 kbits/s in CIF format and 10 kbits/s in QCIF format.

A newly derived algorithm called three-dimensional polynomial approximation coding (3DPAC) is being utilized in the applications of wireless video transmission. After combining the spatial and temporal domain, the video data is organized in a cube form, which has the features of processing parallelism and great compression ratio. Such a very low bit-rate video codec is able to support the wireless data transmission with a bit rate lower than 9.6 kbits/s. The system architecture is presented and an experimental demonstration is also shown. For a video sequence of 176/spl times/144 frame size, a PSNR up to 35 dB may be obtained under 6.5 kbits/s transmission rate.

To overcome the bandwidth limitation and to strengthen the channel effect immunity, a cube-based polynomial video coding scheme for mobile radio transmission is derived, named three-dimensional polynomial approximation coding (3D PAC). It also possesses the features of low bit rate of transmission data, robustness for channel fading and simple computation scheme for real-time processing. Compared with the videophone standard H.261, it gains advantage on resisting channel noise to 2 dB with same bit rate, and the superior subjective performance may be obtained.

Video processing always needs excessive computation which may cause large computing time and thus demands for heavy computing power. It also needs large storage resources and high bandwidth communication channels. Hence, the major objective of video signal processing is to reduce the amount of data computation and use the limited resource bandwidth to handle it. Regression polynomial coding (RPC) is a new compression method based on polynomial coefficients which shapes out the waveform of the block. The computation mechanism employed greatly reduces the computation with serial but not parallel processing, and it is proved that RPC is effective and suitable in low bit rate applications in the environment with limited bandwidth. With the aid of variable length coding to gain more compression, RPC would be a great technique for wireless communications.

An innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient.

An innovative design methodology is proposed for protocol processors design. The protocol description is mapped to statecharts and statecharts are then mapped to a real-time operating system as well as microprocessors. The IS-54 protocol for cellular wireless communication mobile station is taken as the design example. An efficient and easy-for-evaluation design environment is then constructed.

A novel processing scheme for gray level image compression based on the human visual system (HVS) and fuzzy control is proposed. The spatial model of the threshold vision that incorporates the masking processes takes account of two major sensitivities of the human visual system, namely background illumination levels and spatial frequency sensitivities. The distortion measures use common sense fuzzy rules for image quality prediction. The human visual models have been successfully applied in image compression. By the addition of the visual model, performance of these systems has a visible improvement of subject quality depending on visual perception. The processed image performs both improved compression ratio as well as improved SNR (signal to noise ratio) in compression to the standardized still image compression technique, i.e., the JPEG.>

Implementation of the Viterbi decoding algorithm has attracted a great deal of interest in many applications, but the excessive hardware/time consumption caused by the dynamic and backtracking decoding procedures make it difficult to design efficient VLSI circuits for practical applications. A transform algorithm for maximum-likelihood decoding is derived from trellis coding and Viterbi decoding processes. Dynamic trellis search operations are paralleled and well formulated into a set of simple matrix operations referred to as the Viterbi transform (VT). Based on the VT, the excessive memory accesses and complicated data transfer scheme demanded by the trellis search are eliminated. Efficient VLSI array implementations of the VT have been developed. Long constraint length codes can be decoded by combining the processors as the building blocks.>