Advances in the Internet of Things (IoT) have changed Smart Home technology from a local control system to one where many devices with high computational ability are network-enabled. These devices exhibit known and unknown attack surfaces by attackers either compromising the Smart Home itself or exploiting these devices to launch DDoS attacks. However, average home users often lack the technical skills to properly protect their networks and devices from those attacks. And manufacturers tend to design their systems for ease of use rather than ensuring security. Even for skilled home users, secure manual configuration and connection are time-consuming and error-prone. Therefore, it is important to develop a technique which is both simple to manage and secure against cyber-attacks. We present a secure auto-configurable gateway architecture (SAGA) that allows IoT devices to be automatically discovered, registered and configured when they connect to a Smart Home network. SAGA can (1) automatically register IoT devices securely, (2) reject malicious attempts by rogue devices to connect to the network, (3) identify attempts to capture devices by a rogue gateway and (4) provide services such as firewalls, address translation, device software updates, and host home control applications. Security analysis for the proposed architecture and details was performed. A prototype for SAGA was implemented and performance was evaluated in terms of execution/processing time.

The development of cloud computing and big data results in a large amount of data transmitting and storing. In order to protect sensitive data from leakage and unauthorized access, many cryptographic file systems are proposed to transparently encrypt file contents before storing them on storage devices, such as eCryptfs. However, the time-consuming encryption operations cause serious performance degradation. We found that compared with non-crypto file system EXT4, the performance slowdown could be up to 58.53 and 86.89 percent respectively for read and write with eCryptfs. Although prior work has proposed techniques to improve the efficiency of cryptographic file system through computation acceleration, no solution focused on the inefficiency working flow, which is demonstrated to be a major factor affecting system performance. To address this open problem, we present NV-eCryptfs, an asynchronous software stack for eCryptfs, which utilizes NVM as a fast storage tier on top of slower block devices to fully parallelize encryption and data I/O. We design an efficient NVM management scheme to support the fast parallel cryptographic operations. Besides providing an address space that can be directly accessed by the hardware accelerators, our designed mechanism is able to record the memory allocation states, and supplies a backup plan to deal with the situation of NVM shortage. The additional index structure is built to accelerate lookup operations to determine if a given data block resides in NVM. Moreover, we integrate an adaptive scheduling in NV-eCryptfs to process I/O requests dynamically according to access pattern and request size, which is able to take full utilization of both software and hardware acceleration to boost crypto performance. Our evaluation shows the proposed NV-eCryptfs outperforms the original eCryptfs with software routine 23.41× and 5.82× respectively for read and write.

With the rapid development of sensor networks and embedded computing technologies, miniaturized wearable healthcare monitoring devices have become practically feasible. For many of these devices, accelerometer-based user authentication systems by gait analysis are becoming a hot research topic. However, a major bottleneck of such system is it requires continuous sampling of accelerometer, which reduces battery life of wearable sensors. In this paper, we present KEH-Gait, which advocates use of output voltage signal from kinetic energy harvester (KEH) as the source for gait recognition. KEH-Gait is motivated by the prospect of significant power saving by not having to sample the accelerometer at all. Indeed, our measurements show that, compared to conventional accelerometer-based gait detection, KEH-Gait can reduce energy consumption by 82.15 percent. The feasibility of KEH-Gait is based on the fact that human gait has distinctive movement patterns for different individuals, which is expected to leave distinctive patterns for KEH as well. We evaluate the performance of KEH-Gait using two different types of KEH hardware on a data set of 20 subjects. Our experiments demonstrate that, although KEH-Gait yields slightly lower accuracy than accelerometer-based gait detection when single step is used, the accuracy problem can be overcome by the proposed Probability-based Multi-Step Sparse Representation Classification (PMSSRC). Moreover, the security analysis shows that the EER of KEH-Gait against an active spoofing attacker is 11.2 and 14.1 percent using two different types of KEH hardware, respectively.

Indoor localization using radio signals is challenging. A recently proposed algorithm based on WiFi channel state information is an effective solution. However, it relies on a computationally expensive grid search. We propose a new algorithm based on a modified matrix pencil method that reduces the computational complexity by two orders of magnitude without any loss of accuracy.

This work presents a variation of a data collection problem referred as TSP-Data Collection (TSP-DC). Previously we have demonstrated that a two-stage algorithm using Linear-Programming Optimization and Gradient-Descent Optimization (LPO-GDO) is able to solve TSP-DC for minimum tour time. This poster abstract shows that LPO-GDO is also able to solve TSP-DC for an objective function of minimum energy, giving different solutions for different relative energy costs of data transmission and sink movement, and for high or low data loads at sensor nodes.

Face recognition is a hot research topic with a variety of application possibilities, including video surveillance and mobile payment. It has been well researched in traditional computer vision community. However, new research issues arise when it comes to resource constrained devices, such as smart glasses, due to the overwhelming computation and energy requirements of the accurate face recognition methods. In this paper, we propose a robust and efficient sensor-assisted face recognition system on smart glasses by exploring the power of multimodal sensors including the camera and Inertial Measurement Unit (IMU) sensors. The system is based on a novel face recognition algorithm, namely Multi-view Sparse Representation Classification (MVSRC), by exploiting the prolific information among multi-view face images. To improve the efficiency of MVSRC on smart glasses, we propose two novel sampling optimization strategies using the less expensive inertial sensors. Our evaluations on public and private datasets show that the proposed method is up to 10 percent more accurate than the state-of-the-art multi-view face recognition methods while its computation cost is the same order as an efficient benchmark method (e.g., Eigenfaces). Finally, extensive real-world experiments show that our proposed system improves recognition accuracy by up to 15 percent while achieving the same level of system overhead compared to the existing face recognition system (OpenCV algorithms) on smart glasses.

A motion planning algorithm aims to calculate one obstacle-free trajectory which meets the dynamical constraints of a vehicle and leads the vehicle from the start state to the target state. RRT∗ (RRT star) is one sampling-based algorithm which is widely used in many applications because of its speed in quickly finding a trajectory. In contrast with basic RRT (Rapidly-exploring Random Trees) algorithm, RRT∗ improves trajectory optimality significantly by introducing the refinement step after setting up each tree node. This paper describes a new parallel version of the RRT∗ algorithm and its corresponding architecture on an FPGA (Field Programmable Gate Arrays). The refinement step is extracted and runs as a parallel process alongside a continuous tree-extending process. In order to avoid traversing all nodes in every iteration, tree nodes are stored in separate memory blocks and each block is assigned its own tree extending and refining pipelines to enhance the memory throughput. In the experimental evaluation, we take a 3-dimensional state spaces and implement the proposed architecture. The hardware implementation gives a 90 times speed improvement compared with an embedded software implementation, and a 30 times speedup compared to a desktop software implementation.

We consider the problem of self-localization by a resource-constrained mobile node given perturbed anchor position information and distance estimates from the anchor nodes. We consider normally-distributed noise in anchor position information. The distance estimates are based on the log-normal shadowing path-loss model for the RSSI measurements. The available solutions to this problem are based on complex and iterative optimization techniques such as semidefinite programming or second-order cone programming, which are not suitable for resource-constrained environments. In this paper, we propose a closed-form weighted least-squares solution. We calculate the weights by taking into account the statistical properties of the perturbations in both RSSI and anchor position information. We also estimate the bias of the proposed solution and subtract it from the proposed solution. We evaluate the performance of the proposed algorithm considering a set of arbitrary network topologies in comparison to an existing algorithm that is based on a similar approach but only accounts for perturbations in the RSSI measurements. We also compare the results with the corresponding Cramer-Rao lower bound. Our experimental evaluation shows that the proposed algorithm can substantially improve the localization performance in terms of both root mean square error and bias.

Recent years have witnessed a remarkable growth in the number of smart wearable devices. For many of these devices, an important security issue is to establish an authenticated communication channel between legitimate devices to protect the subsequent communications. Due to the wireless nature of the communication and the extreme resource constraints of sensor devices, providing secure, efficient, and user-friendly device pairing is a challenging task. Traditional solutions for device pairing mostly depend on key predistribution, which is unsuitable for wearable devices in many ways. In this article, we design Gait-Key, a shared secret key generation scheme that allows two legitimate devices to establish a common cryptographic key by exploiting users’ walking characteristics (gait). The intuition is that the sensors on different locations on the same body experience similar accelerometer signals when the user is walking. However, one main challenge is that the accelerometer also captures motion signals produced by other body parts (e.g., swinging arms). We address this issue by using the blind source separation technique to extract the informative signal produced by the unique gait patterns. Our experimental results show that Gait-Key can generate a common 128-bit key for two legitimate devices with 98.3% probability. To demonstrate the feasibility, the proposed key generation scheme is implemented on modern smartphones. The evaluation results show that the proposed scheme can run in real time on modern mobile devices and incurs low system overhead.

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. The Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the “cost review” procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. This paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the “exploration” and “review” are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. This work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

Ubiquity of wearable and implantable devices sparks a new set of mobile computing applications that leverage the prolific information of sensors. For many of these applications, to ensure the security of communication between legitimate devices is a crucial problem. In this paper, we design Walkie-Talkie, a shared secret key generation scheme that allows two legitimate devices to establish a common cryptographic key by exploiting users' walking characteristics (gait). The intuition is that the sensors on different locations of the same body experience similar accelerometer signal when the user is walking. However, the accelerometer also captures motion signal produced by other body parts (e.g., swinging arms). We address this issue by employing Blind Source Separation (BSS) technique to extract the informative signal produced by the unique gait pattern. Our experimental results show that the keys generated by two independent devices on the same body are able to achieve up to 100% bit agreement rate. To demonstrate the feasibility, we implement the proposed key generation scheme on modern smartphones. The evaluation results show that the proposed scheme can run in real-time on modern mobile devices and incurs low system overhead.

Face recognition is one of the most popular research problems on various platforms. New research issues arise when it comes to resource constrained devices, such as smart glasses, due to the overwhelming computation and energy requirements of the accurate face recognition methods. In this paper, we propose a robust and efficient sensor-assisted face recognition system on smart glasses by exploring the power of multimodal sensors including the camera and Inertial Measurement Unit (IMU) sensors. The system is based on a novel face recognition algorithm, namely Multi-view Sparse Representation Classification (MVSRC), by exploiting the prolific information among multi-view face images. To improve the efficiency of MVSRC on smart glasses, we propose a novel sampling optimization strategy using the less expensive inertial sensors. Our evaluations on public and private datasets show that the proposed method is up to 10% more accurate than the state-of-the-art multi-view face recognition methods while its computation cost is in the same order as an efficient benchmark method (e.g., Eigenfaces). Finally, extensive real-world experiments show that our proposed system improves recognition accuracy by up to 15% while achieving the same level of system overhead compared to the existing face recognition system (OpenCV algorithms) on smart glasses.

The Rapidly-Exploring Random Trees (RRT) method has been proved successful and efficient for solving path planning problems. Most recent work focuses on optimizing RRT itself and presents the results achieved from software. In this paper a dedicated hardware architecture for FPGA implementation of Rapidly-Exploring Random Tree (RRT) path planning is developed. The proposed architecture fully takes advantage of FPGAs' natural parallel computing ability. The near neighbour (NN) search speed is improved by splitting the whole search space into several sub-spaces; correspondingly the tree nodes are stored in separate block RAMs and each Block RAM owns its independent traversal query module to enhance the memory throughput. Furthermore, to speed up the space exploration, each single path planning unit consists of two cooperating RRT modules which grow trees from each end of the path. One complete path planner involves several path planning units which work in a parallel master-slave mode to increase the probability of obtaining available path. Implementation in a 2D environment shows good path planning performance of the hardware design, with a 30x speed improvement compared to a PC implementation.

Face recognition is one of the most popular research problems on various platforms. New research issues arise when it comes to resource constrained devices, such as smart glasses, due to the overwhelming computation and energy requirements of the accurate face recognition methods. In this paper, we have prototyped a robust and efficient sensor-assisted face recognition system on smart glasses by exploring the power of multimodal sensors including the camera and Inertial Measurement Unit (IMU) sensors. Evaluation shows that the prototyped system is up to 10% more accurate than the state-of-the-art face recognition methods while its computational cost is in the same order as an efficient benchmark method (e.g., Eigenface).

Delay Tolerant Networks (DTN) are characterized by the absence of continuous connectivity resulting in high delivery delays that may exceed the acceptable limit for practical applications. In this paper, we address this issue by introducing Augur. Augur is a new routing protocol for DTNs targeted to minimize delays of message delivery. The routing scheme benefits from the spatiotemporal history data of the nodes to route message s only through gateways having less expected delay to deliver a message to its destination. We demonstrate through a comparative evaluation that Augur outperforms the state of the art DTN protocols in terms of delivery probability, overhead ratio and latency. We found that at low traffic rates Augur reduces the overhead ratio by up to 94%, and by up to 88% at high traffic. We also observed that the improvement in latency was reduced by up to half over the existing protocols in both traffic rates while still improving the delivery probability of messages.

A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application.

Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models.

A new architecture, QUKU, is proposed for implementing stream-based algorithms on FPGAs, which combines the advantages of FPGA and Coarse Grain Reconfigurable Arrays (CGRAs). QUKU consists of a dynamically reconfigurable, coarse-grain Processing Element (PE) array with an associated softcore processor providing system support. At a coarse-grain, the PE array can be reconfigured on a cycle-by-cycle basis to change the PE functionality similarly to that in a conventional CGRA. At a fine-grain, the whole FPGA can be reconfigured statically to implement a completely different PE array that serves the target application in a better way. Advantages of the fine-grain reconfiguration include individually customized PEs, adaptable numeric format support and customizable interconnect network. A prototype CAD tool framework is also developed which facilitates programming the QUKU architecture. An example application consisting of two different image detectors is implemented to demonstrate the advantages of QUKU. QUKU provides up to 140 times speedup and 40 times improvement in area-time product compared to an implementation running on an FPGA-based softcore. The area-time product for QUKU is around 16% lower than that of a custom circuit based implementation on the same FPGA. The per-PE customization provides an area-time saving of approximately 31% compared to a homogeneous 4 × 4 array of PEs for the same application. The experimental results demonstrate that a dual layered reconfigurable architecture provides significant potential benefits in terms of flexibility, area and processing efficiency over existing reconfigurable computing architectures for DSP.

A new project called the Server-Based Internet-Of-Things Architecture (SBIOTA) is introduced. The aim is to develop architectures, protocols, algorithms and services, based on a gateway server, which allow networked devices with extremely limited computation and communications capabilities to participate in the future Internet effectively, efficiently and securely. Key features are the use of a gateway server, the internal use of publish/subscribe messaging and 6lowPAN network layer, and autoconfiguration mechanisms that combine security and ease-of-use.

The employment of device monitoring, diagnosis and condition-based maintenance is one of the potential approaches for enhancing operational efficiency and reducing energy consumption of industrial machines. Industrial wireless sensor networks (IWSNs) for device monitoring are appealing to industry due to their inherent advantages compared with traditional wired systems, such as low cost, convenience of installation and re-location. In this paper, firstly the design requirements of IWSNs are outlined based on surveying application examples and commercial systems. Secondly the wireless protocol standards, current off-the-shelf wireless sensor platforms and prototypes developed by individual researchers for IWSNs are listed and compared. The paper then describes two techniques for improving the efficiency and effectiveness of industrial wireless sensors systems - on-sensor data processing, and a modified MAC protocol for improved real-time performance. Finally possible solutions to deal with particular requirement of IWSNs, including a system architecture and a novel protocol stack for a monitoring system are discussed.

This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.

I: Configuring Algorithms and ProcessesEmbedded computing systems have become an essential part of modern life.Mobile phones are now handheld computers, the automotive industry needs hundreds of embedded processors to build a modern car, and around us are smart sensor systems for monitoring, security, and healthcare, to mention some of them.About 90% of computer applications are embedded systems, most of these are mobile, wireless consumer appliances that must be small in size, with very low power consumption and high performance.Advances in microelectronics have changed the design concepts of embedded application-specific processors.Reconfigurable computing using field programmable gate arrays (FPGAs) have been used for a longtime in embedded digital system design.The reconfiguring is migrating from the circuit level to the level of simple processors and algorithms.The focus in dedicated processor design is no longer merely digital design, it is more reconfigurable multiprocessing.Configurable parallel processing has many advantages.First, it replaces time-consuming digital design by programming of multiprocessors, making the design reprogrammable.Second, mapping algorithms directly onto configurable space of simple processors provides nearly the same efficiency as applicationspecific integrated circuits (ASICs).Third, the multiprocessor concept facilitates the building of energy-efficient systems using dynamic shutdown of unused processors.And last, the performance is scalable, and depends on the algorithmic design, on the number of processors involved, and not on the clock frequency of electrical circuits.Efficient mapping of algorithms onto hardware requires simultaneous study of algorithms and architecture: The algorithm must fit the architecture and the architecture must fit the algorithm.To achieve a best match, one has to be able to (re)configure the architecture as well the algorithms.Coupling this with the multiprocessing requirements where several computational processes are running on the same computational space of elementary processors and connections, and competing for computational resources (processors and connections), a system with dynamic reconfiguration controlled by an operating system is formed.

editorial Free Access Share on Guest editorial CAPA'08 Configurable computing: Configuring algorithms, processes, and architecture Issue II: Configuring hardware architecture Editors: Dr. Toomas P. Plaks Reading University, UK Reading University, UKView Profile , Neil Bergmann Queensland University, Australia Queensland University, AustraliaView Profile , Bernard Pottier University of Bretagne, France University of Bretagne, FranceView Profile Authors Info & Claims ACM Transactions on Embedded Computing SystemsVolume 9Issue 2Article No.: 10pp 1–3https://doi.org/10.1145/1596543.1596544Published:29 October 2009Publication History 0citation248DownloadsMetricsTotal Citations0Total Downloads248Last 12 Months3Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In this paper, we present a reconfigurable system on chip design framework that generates an architectural design along with binding and scheduling algorithm, specific to the input application in Kahn Process Network specification.The likelihood that tasks and communication channels may have many potential physical manifestations is explicitly recognised and embraced, to assist the design exploration process. The architectural design, binding and scheduling problems are formulated as a Integer Linear Programming problem, with physical constraints such as available logic resources, computation time and memory footprints to guide the design space exploration.

In this paper, we present an ILP formulation to assist designers to identify the architectural design, binding schema and scheduling algorithm while satisfying physical constraints such as available logic resources, computation time and memory usage used. Directing the solver to optimise for logic usage, execution time, or other parameters allows ease of exploration of the design space. This case study shows how a proposed ILP formulation solves the design exploration problem in the domain of FPGA-based MPSoC design.

A technique is presented which allows an FPGA-based reconfigurable system-on-chip to automatically and dynamically load hardware peripheral controllers and software device drivers depending on the system's automated identification of peripheral boards which are connected to the FPGA. The technique loads peripheral detection modules into peripheral controller slots at system startup, and after these modules identify the peripheral, the correct hardware controllers and software drivers are loaded.

This paper describes the integration and performance of a multi-stream cipher core with a uClinux Microblaze based reconfigurable system-on- chip that uses the Open Crypto framework. This allows applications to access the multi stream cipher core via kernel space calls.

We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface to enable cross-platform application parallelism on reconfigurable hybrid cluster-on-chip systems and desktop cluster systems. The presented results are promising, showing the suitability, scalability and performance of parallelisation of image processing algorithms with a cross-platform MPI implementation.

We propose an asymmetric multi-processor reconflgurable SoC architecture comprised of a master CPU running embedded Linux and loosely-coupled slave CPUs executing dedicated software processes. The slave processes are mapped into the host OS as ghost processes, and are able to communicate with each other and the master via standard operating system communication abstractions. Custom hardware accelerators can be also added to the slave or master CPUs. We describe an architectural case study of an MP3 decoding application of 12 different single and multi-CPU configurations, with and without custom hardware. Analysis of system performance under master CPU load (computation and IO), and a time-area cost model reveals the counter-intuitive result that multiple CPUs and appropriate software partitioning can lead to more efficient and load-resilient architecture than a single CPU with custom hardware offload capabilities, at a lower design cost.

DSP applications can be suitably represented using process network models. This paper uses a modification of Kahn process network to solve the problem of finding an optimum architectural template for coarse grain array on per application basis. By applying the model at architectural level in QUKU, better hardware efficiency is achieved for a wide domain of applications. A few widely used DSP algorithms have been presented to demonstrate the application of process network models into architectural template generation in QUKU.

This paper presents a network architecture that can be implemented on a reconfigurable System-on-Chip (rSoC) that will accelerate the operation of Virtual Private Networks (VPNs). With a small and efficient 3DES-CBC core coupled the flexibility of the rSoC and a network architecture that can scale as needed, this can be an effective solution to the current real world requirement for a flexible and affordable VPN platform.

In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC cluster community. Additionally the architecture is designed to support native hardware processing modules to participate in the MPI network as fully-fledged peers

The post integration performance of cipher cores to a reconfigurable system-on-chip is a relatively unexplored area. There is also little work done on a stream aware cipher core. This paper presents an architecture that allows a cipher core to operate on multiple cipher streams without context switching. The integration of this architecture using fast simplex links to the microblaze soft-processor is examined in detail. Different communication protocols are examined and the numerical performance of the cipher in uClinux is discussed and analyzed.

Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating systems such as embedded Linux. In reconfigurable system-on-chip (rSoC) design, a critical issue is efficient integration of custom hardware and software resources, where efficiency must be considered in terms of both design time and run time. Process networks communicating via FIFO queues are a powerful model for real time digital system design, especially for data streaming applications such as multimedia devices. FIFOs also form a central part of Unix and Linux interprocess communication (IPC) architectures, where they are more commonly known as pipes. In this paper, we expand on this observation and show how the combination of embedded Linux, reconfigurable system-on-chip, and FIFO communication models provide a compelling platform for efficient design- and run-time implementation of complex, high performance embedded systems.

This paper presents a DES/3DES core that will support cipher block chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.

The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.

Framing protocols employ cyclic redundancy check (CRC) to detect errors incurred during transmission. Generally whole frame is protected using CRC and upon detection of error, retransmission is requested. But certain protocols demand for single bit error correction capabilities for the header part of the frame, which often plays an important role in receiver synchronization. At a speed of 10 Gbps, header error correction implementation in hardware can be a bottleneck. This work presents a hardware efficient way of implementing CRC-16 over 16 bits of data, multiple bit error detection and single bit error correction on FPGA device.

Finite impulse response (FIR) filtering and least mean squares (LMS) adaptive filtering algorithms have been implemented in both hardware and software on a Microblaze processor configured in a Virtex II, running uClinux. These implementations have been evaluated in terms of current usage (both idle and active), area usage (for hardware-assisted implementations), latency and CPU utilisation. Partitioning of the LMS algorithm was initially performed in a simple way, highlighting the shortcomings of obvious partitioning arrangements. A full implementation showed the advantages in terms of increased power efficiency (5.7mA consumed, compared to 60.4mA for the software implementation). Hardware implementations were found to be generally more power efficient, although increased idle power usage (11.3mA extra for the idle LMS implementation) may negate the savings if the task is not executed regularly.

We propose a hybrid rSoC parallel processing architecture consisting of a central 32-bit RISC microprocessor interconnected to an array of 8-bit microcontrollers as coprocessing nodes. The central processor runs an embedded Linux operating system, with the coprocessor nodes mapped into a virtual file system, by which they can be controlled and reprogrammed. The hardware and software architectures are detailed, and several useful application contexts are proposed. Supporting theoretical analysis is also presented.

Embedded systems are an appealing application domain for reconfigurable System-on-Chip (rSoC) technology. However, rSoC design is inherently a complex task with enormous freedom in design parameters such as processor, operating system, and backplane buses. Design efficiency can potentially be improved by the use of an rSoC platform which constrains these choices, and allows new designs to leverage much of the expertise of previous designs. This paper explains and justifies he design decisions for the first version of Egret, which is an rSoC prototyping platform being developed at the University of Queensland, Australia.

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. The paper surveys existing solutions for SoC and analyses the suitability for rSoC application. It also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.

Reconfigurable computing technology (RCT) has provided an alternative to conventional von-Neumann computing which is academically intriguing but of marginal commercial interest to mainstream desktop and supercomputer communities. This paper describes a number of key enabling technologies in the form of an overall design methodology which need to be developed in order to make embedded RCT an effective implementation technology. The paper also describes some first steps that our research group is making in developing these technologies.

Many fast search block-matching motion estimation (BMME) algorithms has been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. We propose a new regular fast search block-matching motion estimation algorithm named two step search (2SS). The 2SS BMME will then be implemented on the SPACE2 custom computer board which consists of up to 8 Xilinx XC6216 fine-grain, sea-of-gate FPGA chips. The experimental and simulation results show that it can have better algorithmic performance and can be implemented by FPGA chips very cost-effectively for video compression applications. Also, the 30 frames per second real time 2SS BMME video compression can be obtained from the SPACE2 custom computer.

Optical character recognition systems improve human-machine interaction and are widely used in many government and commercial departments. After forty years of intensive research, OCR systems for most scripts are well developed. However, not for Arabic script. Since Arabic is a popular script, Arabic OCR systems should have great commercial value. Thus a recognition-based Arabic OCR system is proposed in this paper. It consists of the image acquisition, preprocessing, segmentation, character fragmentation, combination of character fragments, feature extraction, and classification. A signal is fed back to improve and determine the segmentation/recognition result. The system has been implemented and it has 90% recognition accuracy with a 20 chars/sec recognition rate.

This paper describes the implementation of a partially connected neural network using FPGAs (field programmable gate arrays) based custom computers. Starting from the training data, a decision tree is generated using the classifier program C4.5. The tree is then used to initialise the architecture of the neural network to a nearly optimum configuration. This initialised partially connected network is then trained using training data. The trained neural network is then implemented by fine-grain Xilinx XC6200 series FPGAs. This implementation requires fewer connections and can provide a very high speed classification for many real-time image recognition applications.

The discrete cosine transform (DCT) is a key step in many image and video coding applications, and its efficient implementation has been extensively studied for software implementations and for custom VLSI. We analyse the use of the distributed arithmetic algorithm for the efficient implementation of the DCT in reconfigurable logic.

The field programmable gate array (FPGA) based custom computer is a new computing paradigm which can provide fast and flexible processing. This paper describes the implementation of 2D DCT algorithms for video compression using a FPGA-based custom computer. Our experimental result shows that by using an FPGA-based custom computer, the speed for processing 2D discrete cosine transforms in video compression can be improved 50 to 100 times when compared with workstation or super-computer implementations.

We analyse eighteen months of national and international deployment of a prototype telemeeting system supporting synchronous remote meetings which make extensive use of shared documents as well as video and audio conferencing. Logistics of a telemeeting include scheduling people and equipment, document format conversion, pre-sending documents, training, equipment and call setup, and meeting followup. The logistics burden is much larger than expected and can be a barrier to adoption of telemeeting technology. Using a process model that recognises moving between solo and group, asynchronous and synchronous work modes, the paper explores the amenability of individual logistics tasks to automated assistance, proposes a framework for such assistance, and develops a set of design principles.

Field programmable gate arrays (FPGAs) can be rapidly reconfigured to provide different digital logic functions. When such FPGA logic circuits are incorporated within a stored-program computer, the result is a machine where the programmer can design both the software and the hardware that will execute that software. This paper first surveys this area of custom computing. It then describes a new custom computing architecture which uses a processing node with three sections: a standard arithmetic chip, static RAM and reconfigurable logic for operand handling. Finally an analysis of the suitability of this new approach for implementation of DSP applications shows it to be worthy of further investigation.>

A new and novel CMOS IC design methodology is presented which allows a single design representation, captured at the symbolic level, to be implemented in different classes of CMOS fabrication technologies such as N-well, P-well, Twin-well and SOI. Extensive use is made of CAD tools to achieve automatic conversion from the technology independent representation into process specific mask sets, and some of the algorithms used in these tools are outlined in the paper.