Samsung Pay, a widely-used mobile payment service, enables users to pay using just their smartphone thanks to Magnetic Secure Transmission (MST). This technology facilitates communication between smartphones and magnetic card terminals by transmitting payment tokens through magnetic waves. Intriguingly, such magnetic waves inherently produce a distinct sound pattern (calledMST sound) containing payment information, which opens up new opportunities for both potential attackers and payment users. That is, MST sound can serve either as a new side channel for attackers to eavesdrop on MST transactions or as an easily accessible communication channel that enhances the payment experience for users. Inspired by these possibilities, we aim to deeply explore the potential of MST sound across these two dimensions, presenting two frameworks with different objectives: MagSnoop and M2APay. The first is the inference framework, which accurately, robustly, and efficiently infers payment tokens by listening to MST sounds. The second is the payment framework, which helps users establish a secure communication channel between MST-supported smartphones and microphone-equipped smartphones by shielding the vulnerability inherent in MST sound. Our experiments with prototypes of these frameworks achieved high accuracy in token inference and data transmission. Furthermore, both MagSnoop and M2APay are capable of accurately decoding tokens in diverse payment environments, including noisy environments and real-world scenarios.

In this paper, we present TapAuth, a novel smartphone user authentication system that leverages vibrations generated from a user's tap inputs. TapAuth is based on the observation that the vibrations have their unique characteristic depending on the user due to differences in finger structure. Specifically, TapAuth collects audio and motion data using only built-in sensors, while users are entering PIN code. Then, it authenticates the user by verifying the validity of the code and comparing the collected data with a pre-built training dataset. Our experimental results with 20 real-world users show that TapAuth can achieve high accuracy.

Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, in this article, we propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime. Precisely, 1) we formulate the problem of finding an efficient configuration of monitoring circuits into an instance of optimal experiment design problem and 2) propose a new timing prediction flow, consisting of statistical estimation of FEOL and BEOL process variations and a neural network-based timing inference model. For accurate control of timing margin and overcoming simulation-silicon discrepancies, 3) we introduce uncertainty learning in the prediction model construction and calibrate it through transfer learning. Furthermore, 4) we avoid time-consuming SPICE simulations in our methodology by employing efficient but accurate surrogate models. Through simulations using a 28-nm industry PDK and DK characterized at 0.6-V operation, it is shown that our methodology is highly effective, reducing the average prediction pessimism of maximum delay by 77.9% over conventional signoff results while respecting target prediction yield. Besides, for test chips fabricated using a 10-nm process, we demonstrated that our holistic approach from design to postsilicon phase in conjunction with adaptive voltage scaling reduces dynamic power consumption by 28.2%–28.8% on average, in comparison with typical supply voltage operation.

In this work, we address the synthesis problem of two-phase bundled-data asynchronous pipeline controllers, in which the insertion of buffers is essential for guaranteeing the correct handshaking operation on every pipeline stage at the expense of considerable area increase. To lighten the pipeline controllers, we introduce a new logic synthesis concept called delay path sharing and reusing, by which we can significantly reduce the amount of the costly delay buffers. Precisely, first, we propose a technique of synthesizing an asynchronous pipeline controller in a way to share delay buffers among setup timing paths on pipeline stages for minimally allocating total delay buffers. In addition, we devise an area-efficient delay circuit structure called delay path unit (DPU) by extending the proposed delay path sharing concept and propose an in-depth synthesis flow of an asynchronous pipeline controller using DPUs. Through experiments with benchmark circuits using a 45-nm cell library, it is shown that our techniques of synthesizing asynchronous pipeline controllers are able to reduce the controller area by up to 46.3%-59.4% and the leakage power by up to 33.0%-49.0% on average while retaining the same level of performance.

An elaborate hardware performance monitor (HPM) has become increasingly important for handling huge performance variation of near-threshold computing and recent process technologies. In this paper, we propose a new approach to the problem of predicting critical path delays (CPDs) using HPM. Precisely, for a target circuit or system, we formulate the problem of finding an efficient combination of ring oscillators (ROs) for accurate prediction of CPDs on the circuit as a mixed integer second-order cone programming and propose a method of minimizing the total number of ROs for a given pessimism level of prediction. Then, we propose a prediction flow of CPDs through statistical estimation of process parameters from measurements of the customized HPM and machine learning based delay mapping from the estimation. For a set of benchmark circuits tested using 28nm PDK and 0.6V operation, it is shown that our approach is very effective, reducing the pessimism of CPDs and minimum supply voltages by 6.7~52.9% and 20.6~50.8% over those of conventional approaches, respectively.

A bundled-data asynchronous circuit is a promising alternative to a synchronous circuit for implementing high performance low power systems, but it requires to deploy special circuitry to support the asynchronous communication between every pair of consecutive pipeline stages. This work addresses the problem of reducing the size of asynchronous pipeline controller. Lightening the pipeline controller directly impacts two critical domains: (1) it mitigates the increase of controller area caused by high process-voltage-temperature variation on circuit; (2) it contributes to proportionally reducing the leakage power. (Note that a long delay in circuit between pipeline stages requires a long chain of delay elements in the controller.) Precisely, we analyze the setup timing paths on the conventional asynchronous pipeline controller, and (i) resynthesize new setup timing paths, which allows to share some of the expensive delay elements among the paths while assuring the communication correctness. Then, we (ii) optimally solve the problem of minimizing the number of delay elements by formulating it into a linear programming. For a set of test circuits with a 45nm standard cell library, it is shown that our synthesis and optimization method reduces the total area of delay elements and the leakage power of pipeline controller by 46.4% and 43.6% on average, respectively, while maintaining the same level of performance and dynamic power consumption.