Understanding cultural heritage through technology faces challenges in connecting with diverse audiences, especially when interpreting art across cultures. In this work, we present CultiVerse, a visual analytics system that leverages Large Language Models (LLMs) to support cross-cultural appreciation of Traditional Chinese Paintings (TCPs). CultiVerse operates within a mixed-initiative framework and guides users through three stages: extracting cultural context, aligning cross-cultural symbols, and extrapolating meaning in the viewer's cultural frame. By combining an interactive interface with LLM-powered analysis, the system enables deeper engagement with symbolic meanings and encourages serendipitous cross-cultural discoveries. Our approach bridges AI interpretation and human insight to foster mutual understanding in a multicultural setting. A curated TCP dataset supports exploration, while empirical evaluations confirm that CultiVerse enhances user understanding, interpretation accuracy, and cultural empathy.

Symmetry and matching between critical building blocks have a significant impact on analog system performance. However, there is limited research on generating system level symmetry constraints. In this paper, we propose a novel method of detecting system symmetry constraints for analog circuits with graph similarity. Leveraging spectral graph analysis and graph centrality, the proposed algorithm can be applied to circuits and systems of large scale and different architectures. To the best of our knowledge, this is the first work in detecting system level symmetry constraints for analog and mixed-signal (AMS) circuits. Experimental results show that the proposed method can achieve high accuracy of 88.3% with low false alarm rate of less than 1.1% in largescale AMS designs.

Existing analog layout synthesis tools provide little guarantee to post layout performance and have limited capabilities of handling system-level designs. In this paper, we present a closed-loop hierarchical analog layout synthesizer, capable of handling system designs. To ensure system performance, the building block layout implementations are optimized efficiently, utilizing post layout simulations with multi-objective Bayesian optimization. To the best of our knowledge, this is the first work demonstrating success in automated layout synthesis on generic analog system designs. Experimental results show our synthesized continuous-time ΔΣ modulator (CTDSM) achieves post layout performance of 65.9dB in signal to noise and distortion ratio (SNDR), compared with 67.8dB in the schematic design.

Optical neural network (ONN) is a neuromorphic computing hardware based on optical components. Since its first on-chip experimental demonstration, it has attracted more and more research interests due to the advantages of ultra-high speed inference with low power consumption. In this work, we design a novel slimmed architecture for realizing optical neural network considering both its software and hardware implementations. Different from the originally proposed ONN architecture based on singular value decomposition which results in two implementation-expensive unitary matrices, we show a more area-efficient architecture which uses a sparse tree network block, a single unitary block and a diagonal block for each neural network layer. In the experiments, we demonstrate that by leveraging the training engine, we are able to find a comparable accuracy to that of the previous architecture, which brings about the flexibility of using the slimmed implementation. The area cost in terms of the Mach-Zehnder interferometers, the core optical components of ONN, is 15%-38% less for various sizes of optical neural networks.

In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we propose a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. Experimental results show that the proposed technique is able to generate wells close to manual designs with comparable post-layout circuit performance.

Photonic integrated circuit (PIC), as a promising alternative to traditional CMOS circuit, has demonstrated the potential to accomplish on-chip optical interconnects and computations in ultra-high speed and/or low power consumption. Wavelength division multiplexing (WDM) is widely used in optical communication for enabling multiple signals being processed and transferred independently. In this work, we apply WDM to optical logic PIC synthesis to reduce the PIC area.

Despite tremendous advancement of digital IC design automation tools over the last few decades, analog IC layout is still heavily manual which is very tedious and error-prone. This paper will first review the history, challenges, and current status of analog IC layout automation. Then, we will present MAGICAL, a human-intelligence inspired, fully-automated analog IC layout system currently being developed under the DARPA IDEA program. It starts from an unannotated netlist, performs automatic layout constraint extraction and device generation, then performs placement and post-placement optimization, followed by routing to obtain the final GDSII layout. Various analytical, heuristic, and machine learning algorithms will be discussed. MAGICAL has obtained promising preliminary results. We will conclude the paper with further discussions on challenges and future directions for fully-automated analog IC layout.

Due to sensitive layout-dependent effects and varied performance metrics, analog routing automation for performance-driven layout synthesis is difficult to generalize. Existing research has proposed a number of heuristic layout constraints targeting specific performance metrics. However, previous frameworks fail to automatically combine routing with human intelligence. This paper proposes a novel, fully automated, analog routing paradigm that leverages machine learning to provide routing guidance, mimicking the sophisticated manual layout approaches. Experiments show that the proposed methodology obtains significant improvements over existing techniques and achieves competitive performance to manual layouts while being capable of generalizing to circuits of different functionality.

The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically different from their digital counterparts. AMS circuit layouts usually include a variety of devices, including transistors, capacitors, resistors, and inductors. A complicated AMS IC system with hierarchical structure may also consist of pre-laid out subcircuits. Different types of devices can occupy different manufacturing layers. Therefore, during the layout stage, the devices require co-optimization to achieve high circuit performance. Leveraging the fact that some devices can be built by mutually exclusive layers, they can be carefully designed to overlap each other to effectively reduce the total area and wirelength without degrading the circuit performance. In this paper, we propose an analytical framework to tackle the device layer-aware analog placement problem. Experimental results show that on average the proposed techniques can reduce the total area and half-perimeter wirelength by 9% and 23%, respectively. To verify the routability of the placement results, we also develop an analog global router, which demonstrates that the device layer-aware placement can achieve 18% shorter wirelength during global routing.

In analog/mixed-signal (AMS) integrated circuits (ICs), most of the layout design efforts are still handled manually, which is time-consuming and error-prone. Given the previous high-quality manual layouts containing valuable design expertise of experienced designers, exploring layout design constraints from the existing layouts is desirable. In this paper, we extract and explore analog placement constraints from previous quality-approved layouts, including regularity and symmetry (symmetry-island) constraints. For the first time, an efficient sweep line-based algorithm is developed to comprehensively extract the regularity constraints in a given analog placement, which can not only improve routability but also minimize the layout parasitics-induced circuit performance degradation. Furthermore, we propose a novel layout technology migration and performance retargeting framework, where we apply the constraint extraction algorithms to improve the placement quality while preserving previous design expertise. Experimental results show that the proposed techniques can preserve the symmetry and regularity constraints, and also reduce the placement area by 7.6% on average.

Conventional analog/mixed-signal (AMS) circuits design methodology relying heavily on the use of operational amplifiers (opamps) to process signals in voltage-domain (VD) encounters severe difficulties in advanced nanometer-scale CMOS process. We present a novel scaling compatible, synthesis friendly ring voltage-controlled oscillator (VCO) based time-domain (TD) delta-sigma analog-to-digital converter (ADC) whose performance improves as technology advances. Decomposed into digital gates (e.g. inverters) and a small set of simple customized cells (e.g. resistors), its layout is fully synthesizable by leveraging digital layout synthesis tools. Post-layout simulation results demonstrate the scaling compatibility of the proposed ADC and a drastic boost to design productivity.

High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net wire length minimization should be considered during placement, in addition to the conventional optimization objectives of total area and half perimeter wire length (HPWL). In this paper, we develop effective hierarchical and analytical techniques for high-performance analog circuits placement, which is a complex problem given its multi-objectives and constraints (e.g. hierarchical symmetric groups). The entire circuit is first partitioned hierarchically in a top-down, critical parasitics aware, hierarchical symmetric constraints and proximity constraints feasible manner, where the placement subproblem for each partition at each level can be solved in reasonable run-time. Then, different placement variants are generated for each partition from bottom up, taking advantage of the computation power of modern multi-core systems with parallelization. To assemble the placement variants of different subpartitions, a Mixed Integer Linear Programming (MILP) formulation is proposed which can simultaneously minimize critical parasitic loading, total area and HPWL, and handle hierarchical symmetric constraints, module variants selection and orientation. Experimental results demonstrate the effectiveness of the proposed techniques.

Triple patterning lithography (TPL) is one of the most promising lithography technology in sub-14-nm technology nodes, especially for complicated low metal layer manufacturing. To overcome the intracell routability problem and improve the cell regularity, recently middle-of-line (MOL) layers are employed in standard cell design. However, MOL layers may introduce a large amount of cross-row TPL conflicts for row-based design. Motivated by this challenge, in this paper we propose the first TPL aware detailed placement toward zero cross-row MOL conflict. In standard cell precoloring, Boolean-based look-up table is proposed to reduce solution space. In detailed placement stage, three powerful techniques, i.e., local reordered single row refinement, min-cost flow-based conflict removal, and local cell interleaving, are proposed to provide zero TPL conflict solution. The experimental results demonstrate the effectiveness of our proposed methodologies.

Triple patterning lithography (TPL) is one of the most promising lithography technology in sub-14nm technology nodes, especially for complicated low metal layer manufacturing. To overcome the intra-cell routability problem and improve the cell regularity, recently middle-of-line (MOL) layers are employed in standard cell design. However, MOL layers may introduce a large amount of cross-row TPL conflicts for row based design. Motivated by this challenge, in this paper we propose the first TPL aware detailed placement toward zero cross-row MOL conflict. In standard cell pre-coloring, boolean based look-up table is proposed to reduce solution space. In detailed placement stage, two powerful techniques, i.e., local reordered single row refinement (LRSR) and min-cost flow based conflict removal, are proposed to provide zero TPL conflict solution. The experimental results demonstrate the effectiveness of our proposed methodologies.