Demo Data from VLDB 2026 / reviewers in the wild / expert
Marina Neseem
dblp:241/4289
· DBLP profile ↗
6ranked-venue papers
3as first author
4since 2021 · last 2024
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 2 since 2021Artificial intelligence and machine learning · 2 · 1 first-author · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 46% Electronic design automation · 23% Performance modeling and evaluation · 23% | |
| Artificial intelligence
2 papers |
Efficient and distributed learning · 72% Learning paradigms · 28% | |
| Human-computer interaction and pervasive computing
1 paper |
Ubiquitous computing and smart environments · 100% |
Topics — the 12 heaviest of 13, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Efficient and distributed learning › parameter-efficient fine-tuning
low-rank adaptation |
0.8 | 1 | 2024 | MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning · CVPR 2024 |
Machine learning › Learning paradigms
multi-task learning |
0.8 | 1 | 2024 | MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning · CVPR 2024 |
Machine learning › Efficient and distributed learning
parameter-efficient fine-tuning |
0.8 | 1 | 2024 | MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning · CVPR 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
low-precision DNN inference |
0.8 | 1 | 2024 | PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks · CVPR 2024 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks · CVPR 2024 |
Ubiquitous computing and smart environments › context recognition
activity recognition |
0.4 | 1 | 2020 | AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices · DAC 2020 |
Electronic design automation
logic synthesis |
0.4 | 1 | 2019 | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project · DAC 2019 |
Electronic design automation
physical design |
0.4 | 1 | 2019 | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project · DAC 2019 |
Machine learning › Efficient and distributed learning
model compression |
0.2 | 1 | 2024 | PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks · CVPR 2024 |
Machine learning › Efficient and distributed learning › model compression
quantization |
0.2 | 1 | 2024 | PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks · CVPR 2024 |
Energy-efficient computing › low-power design
low-power sensing |
0.1 | 1 | 2020 | AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices · DAC 2020 |
Cloud and datacenter computing
cloud deployment |
0.1 | 1 | 2019 | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project · DAC 2019 |
Methods — techniques the papers use, named apart from their topics
quantization · 1.5double quantization · 1.5distribution-heterogeneous quantization · 1.5sensor configuration switching · 0.9feature extraction · 0.9classification · 0.9low-rank adaptation · 0.8hierarchical transformer · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task LearningabstractAdapting models pre-trained on large-scale datasets to a variety of downstream tasks is a common strategy in deep learning. Consequently, parameter-efficient fine-tuning methods have emerged as a promising way to adapt pretrained models to different tasks while training only a minimal number of parameters. While most of these methods are designed for single-task adaptation, parameter-efficient training in Multi-Task Learning (MTL) architectures is still unexplored. In this paper, we introduce MTLoRA, a novel framework for parameter-efficient training of MTL models. MTLoRA employs Task-Agnostic and Task-Specific Low-Rank Adaptation modules, which effectively disentangle the parameter space in MTL fine-tuning, thereby enabling the model to adeptly handle both task specialization and interaction within MTL contexts. We applied MTLoRA to hierarchical-transformer-based MTL architectures, adapting them to multiple downstream dense prediction tasks. Our extensive experiments on the PASCAL dataset show that MTLoRA achieves higher accuracy on downstream tasks compared to fully fine-tuning the MTL model while reducing the number of trainable parameters by 3.6×. Furthermore, MTLoRA establishes a Pareto-optimal trade-off between the number of trainable parameters and the accuracy of the downstream tasks, outperforming current state-of-the-art parameter-efficient training methods in both accuracy and efficiency. Our code is publicly available.11https://github.com/scale-lab/MTLoRA.git Ahmed Agiza, Marina Neseem, Sherief Reda |
CVPR | 2 |
| 2024 | PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural NetworksabstractLow-precision quantization is recognized for its efficacy in neural network optimization. Our analysis reveals that non-quantized elementwise operations which are prevalent in layers such as parameterized activation functions, batch normalization, and quantization scaling dominate the inference cost of low-precision models. These non-quantized elementwise operations are commonly overlooked in SOTA efficiency metrics such as Arithmetic Computation Effort (ACE) [46]. In this paper, we propose ACEv2- an extended version of ACE which offers a better alignment with the inference cost of quantized models and their energy consumption on ML hardware. Moreover, we introduce PikeLPN11Pike is a slim fast fish, LPN stands for Low-Precision Network., a model that addresses these efficiency issues by applying quantization to both elementwise operations and multiply-accumulate operations. In particular, we present a novel quantization technique for batch normalization layers named QuantNorm which allows for quantizing the batch normalization parameters without compromising the model performance. Additionally, we propose applying Double Quantization where the quantization scaling parameters are quantized. Furthermore, we recognize and resolve the issue of distribution mismatch in Separable Convolution layers by introducing Distribution-Heterogeneous Quantization which enables quantizing them to low-precision. PikeLPN achieves Pareto-optimality in efficiency-accuracy trade-off with up to 3× efficiency improvement compared to SOTA low-precision models. Marina Neseem, Conor McCullough, Randy Hsin, Chas Leichner, Shan Li 0001, In Suk Chong, Andrew G. Howard, Lukasz Lew, Sherief Reda, Ville-Mikko Rautio, Daniele Moro |
CVPR | 1 |
| 2021 | AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded DevicesabstractConvolutional Neural Networks achieve state-of-the-art accuracy in object detection tasks. However, they have large computational and energy requirements that challenge their deployment on resource-constrained edge devices. Object detection takes an image as an input, and identifies the existing object classes as well as their locations in the image. In this paper, we leverage the prior knowledge about the probabilities that different object categories can occur jointly to increase the efficiency of object detection models. In particular, our technique clusters the object categories based on their spatial co-occurrence probability. We use those clusters to design an adaptive network. During runtime, a branch controller decides which part(s) of the network to execute based on the spatial context of the input frame. Our experiments using COCO dataset show that our adaptive object detection model achieves up to 45% reduction in the energy consumption, and up to 27% reduction in the latency, with a small loss in the average precision (AP) of object detection. Marina Neseem, Sherief Reda |
ICCAD | 1 |
| 2021 | Sparse Bitmap Compression for Memory-Efficient Training on the Edge
Abdelrahman Hosny, Marina Neseem, Sherief Reda |
SEC | 2 |
| 2020 | AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable DevicesabstractWearable devices have strict power and memory limitations. As a result, there is a need to optimize the power consumption on those devices without sacrificing the accuracy. This paper presents AdaSense: a sensing, feature extraction and classification co-optimized framework for Human Activity Recognition. The proposed techniques reduce the power consumption by dynamically switching among different sensor configurations as a function of the user activity. The framework selects configurations that represent the pareto-frontier of the accuracy and energy trade-off. AdaSense also uses low-overhead processing and classification methodologies. The introduced approach achieves 69% reduction in the power consumption of the sensor with less than 1.5% decrease in the activity recognition accuracy. Marina Neseem, Jon Nelson, Sherief Reda |
DAC | 1 |
| 2019 | Toward an Open-Source Digital Flow: First Learnings from the OpenROAD ProjectabstractWe describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system designers today. The development of open-source, self-driving design tools is in and of itself a "moon shot" with numerous technical and cultural challenges. The open-source flow incorporates a compatible open-source set of tools that span logic synthesis, floorplanning, placement, clock tree synthesis, global routing and detailed routing. The flow also incorporates analysis and support tools for static timing analysis, parasitic extraction, power integrity analysis, and cloud deployment. We also note several observed challenges, or "lessons learned", with respect to development of open-source EDA tools and flows. Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu |
DAC | 10 |