This paper focuses on how smart technologies integrated in a one-family home, and particularly a window, offer unique challenges and opportunities for designing buildings with the best possible environments for people and nature. Toward an interdisciplinary and multidimensional approach, we address the interaction between daylight defined in technical terms and daylight defined in aesthetic, architectural terms. Through field tests of a Danish carbon-neutral home and an analysis of five key design parameters, we explore the contradictions and potentials in smart buildings, using the smart window as an example of how quality of life and technical advances are synthesized and when they contradict. We focus on the need to define quantitative and qualitative values and synthesize these in a multidimensional design approach, toward allowing the house to adapt to a changing climate, satisfy the human needs of the occupants, together with meeting calculated energy requirements. Thus, integrating windows as key design elements in energy-positive buildings addresses aesthetic as well as technical potentials. This integration of factors from different fields can both support and counterbalance one another in the design process. We maintain that a hybrid approach to the energy design is central. The study illuminates an approach of the design of smart houses as living organisms by connecting technology with the needs of the occupants with the power and beauty of daylight.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm/sup 2/, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method.