The paper presents pp-mess-sim, an object-oriented discrete-event simulation environment for evaluating interconnection networks in message-passing systems. The simulator provides a toolbox of various network topologies, communication workloads, routing-switching algorithms, and router models. By carefully defining the boundaries between these modules, pp-mess-sim creates a flexible and extensible environment for evaluating different aspects of network design. The simulator models emerging multicomputer networks that can support multiple routing and switching schemes simultaneously; pp-mess-sim achieves this flexibility by associating routing-switching policies, traffic patterns, and performance metrics with collections of packets, instead of the underlying router model. Besides providing a general framework for evaluating router architectures, pp-mess-sim includes a cycle-level model of the PRC, a programmable router for point-to-point distributed systems. The PRC model captures low-level implementation details, while another high-level model facilitates experimentation with general router design issues. Sample simulation experiments capitalize on this flexibility to compare network architectures under various application workloads.

Modern parallel and distributed applications have a wide range of communication characteristics and performance requirements. This paper presents programmable routing controller (PRC), a custom ASIC that supports flexible network policies to accommodate diverse application requirements. By dedicating a small programmable processor to each incoming link, the PRC can implement wormhole, virtual cut-through, and packet switching, as well as hybrid schemes, under a variety of unicast and multicast routing algorithms. The PRC can support several applications or traffic types simultaneously by implementing multiple routing-switching microcode routines.

SPIDER is a network adapter that provides scalable communication support for point-to-point distributed systems. The device exports an efficient interface to the host processor, provides transparent support for dependable, time-constrained communication, and handles packet routing and switching. The communication support provided by SPIDER exploits concurrency between the independent data channels feeding the point-to-point network, and offers flexible and transparent hardware mechanisms. SPIDER allows the host to exercise fine-grain control over its operation, enabling the latter to monitor and influence data transmission and reception efficiently. In the current implementation, SPIDER interfaces to the Ironics IV-3207, a VMEbus-based 68040 card and will be controlled by x-kernel, a communication executive allowing the flexible composition of communication protocols.>

While researchers strive to develop new systems to enhance the cooperative document editing process, many authors already collaborate, using existing text processing systems to produce papers and reports. Using these tools, one of the most time-consuming and error-prone collaboration tasks is maintaining a consistent shared bibliography. We have designed and implemented the BIBDB system to simplify collaborative authoring by providing a shared, cooperatively maintained bibliographicdatabase. BIBDB uses existing networking technology and merges seamlessly into the LTEX/BIBTEX text processing system [5]. The contributions of BIBDB include a set of user interface policies and software implementation techniques that support cooperative database maintenance.

The authors present a formal analysis of virtual cut-through in a C-wrapped hexagonal mesh multicomputer, called the HARTS (hexagonal architecture for real-time systems). In virtual cut-through, packets arriving at an intermediate node are forwarded to the next node in the route without buffering if a circuit can be established to the next node. The hexagonal mesh is first characterized using a combinatorial analysis to determine the probability that a packet will establish a cut-through at an intermediate node. Given this parameter the probability distribution function for packet delivery times in HARTS is derived. The delivery times obtained from the analytic model are then compared against results collected from a simulator of the routing hardware designed for use in HARTS. The results from both the analytic model and the simulator further reinforce the choice of the virtual cut-through routing scheme for use in HARTS.>

The design and implementation of a VLSI routing controller for use in the Hexagonal Architecture for Real-Time Systems (HARTS), which is currently being built, are presented. The routing controller is a microprogrammed unit designed to function as an intelligent front-end interface for the interconnection network. Unlike other routine controllers known to date, this routing controller allows for the flexibility to investigate several low-level routing algorithms by downloading the appropriate microcode into the routing controller. The design was carried out using the combination of Seattle Silicon Technology's silicon compiler and Mentor Graphic's schematic capture and simulation tools. The implementation is targeted for a 64-pin package using a 1.2- mu m CMOS process.>