Digital Twin (DT) is a revolutionary technology changing how a smart manufacturing industry carries out its day-to-day activities. DT can provide numerous advantages such as real-time synchronised functioning, monitoring and data analysis. However, security and privacy issues in DT have not been thoroughly investigated. This article proposes a user-empowerment-based privacy-preserving authentication protocol for a cloud-based Digital Twin using a Decentralised Identifier (DID) and Verifiable Credential (VC). Here, user empowerment provides full control to users over their identities, and with the help of VC, users can prove their authenticity and preserve their privacy. Although DID has emerged as a promising technology for introducing user empowerment, it suffers from some fundamental problems such as usability and auditability. Here we address all these issues and propose a user-revocation-enabled security solution for the DT. A security analysis of the proposed scheme shows that it is secured against significant security threats. With the help of performance analysis, we prove that the proposed work effectively ensures security and privacy in DT.

Underwater Acoustic Sensor Networks (UW-ASNs) are predominantly used for underwater environments and find applications in many areas. However, a lack of security considerations, the unstable and challenging nature of the underwater environment, and the resource-constrained nature of the sensor nodes used for UW-ASNs (which makes them incapable of adopting security primitives) make the UW-ASN prone to vulnerabilities. This paper proposes an Adaptive decentralised Intrusion Detection and Prevention System called AIDPS for UW-ASNs. The proposed AIDPS can improve the security of the UW-ASNs so that they can efficiently detect underwater-related attacks (e.g., blackhole, grayhole and flooding attacks). To determine the most effective configuration of the proposed construction, we conduct a number of experiments using several state-of-the-art machine learning algorithms (e.g., Adaptive Random Forest (ARF), light gradient-boosting machine, and K-nearest neighbours) and concept drift detection algorithms (e.g., ADWIN, kdqTree, and Page-Hinkley). Our experimental results show that incremental ARF using ADWIN provides optimal performance when implemented with One-class support vector machine (SVM) anomaly-based detectors. Furthermore, our extensive evaluation results also show that the proposed scheme outperforms state-of-the-art bench-marking methods while providing a wider range of desirable features such as scalability and complexity.

Internet of Things (IoT)- based services connect the user with sensing devices through intermediary devices like a gateway. The authentication with secure key exchange assures security trio of confidentiality, integrity, and availability for the complete IoT-based system. It also ensures trusted privacy of communicated information. Recently, numerous authors proposed a Remote User Authentication scheme (RUA) on User-Gateway based secure key exchange for the tiny and lightweight sensor based paradigms such as an IoT and a wireless sensor network (WSN) using lightweight mathematical approaches. In this article, we propose a reliable and efficient lightweight key exchange scheme with the secure RUA for the user-gateway model. For designing a lightweight RUA scheme, we use elliptic curve cryptography (ECC). We use BAN-Logic for the validation of mutual authentication. We use widely accepted random oracle-based ROR model for formal security analysis and Dolev-Yao channel for informal security analysis. For the implementation and result collection of the proposed scheme, we used publisher-subscriber-based lightweight Message Queuing Telemetry Transport (MQTT) protocol. Overall, in this article, we propose a highly secure and efficient RUA scheme for the sensor-based environment with the formal security analysis and real-time implementation.

There has been a lot of recent interest in applying machine learning (ML) to the design of systems, which purports to aid human experts in extracting new insights leading to better systems. In this work, we share our experiences with applying ML to improve one aspect of networks-on-chips (NoC) to uncover new ideas and approaches, which eventually led us to a new arbitration scheme that is effective for NoCs under heavy contention. However, a significant amount of human effort and creativity was still needed to optimize just one aspect (arbitration) of what is only one component (the NoC) of the overall processor. This leads us to conclude that much work (and opportunity!) remains to be done in the area of ML-driven architecture design.

Embedded systems are prone to leak information via side-channels associated with their physical internal activity, such as power consumption, timing, and faults. Leaked information can be analyzed to extract sensitive data and devices should be assessed for such vulnerabilities. Side-channel power-supply leakage from embedded devices can also provide information regarding instruction-level activity for control code executed on these devices. Methods proposed to disassemble instruction-level activity via side-channel leakage have not addressed issues related to pipelined multi-clock-cycle architectures, nor have proven robustness or reliability. The problem of detecting malicious code modifications while not obstructing the sequence of instructions being executed needs to be addressed. In this article, instruction sequences being executed on a general-purpose pipelined computing platform are identified and instructions that make up these sequences are classified based on hardware utilization. Individual instruction classification results using a fine-grained classifier is also presented. A dynamic programming algorithm was applied to detect the boundaries of instructions in a sequence with a 100 percent accuracy. A unique aspect of this technique is the use of multiple power supply pin measurements to increase precision and accuracy. To demonstrate the robustness of this technique, power leakage data from ten target FPGAs programmed with a prototype of the pipelined architecture was analyzed and classification accuracies averaging 99 percent were achieved with instructions labeled based on hardware utilization. Individual instruction classification accuracies above 90 percent were achieved using a fine-grained classifier. Classification accuracies were also verified when a target FPGA was subjected to different controlled temperatures. The classification accuracies on discrete (ASIC) pipelined-architecture microcontrollers was 97 percent.

This paper presents a low power, domain-specific manycore accelerator referred to as "BiNMAC"- Binarized neural Network Manycore ACcelerator, which effectively maps and executes Binary Deep Neural Networks (BNNs). With only 2.40% and 1.88% area and power overhead, novel instructions such as Population-Count and Patch-Select are added to the ISA of the BiNMAC, each of which replaces frequently used functions that would have taken 52 and 4 clock cycles respectively with 1 clock cycle. A 64-cluster architecture of the BiNMAC is fully placed and routed in 65~nm TSMC CMOS technology, where a single cluster occupies an area of 0.53 mm^2 with a power of 223 mW at 1 GHz clock frequency. The 64-cluster architecture takes 36.5 mm^2 area and, if fully utilized, consumes a power of 16.4 W. We also propose a multilayer perceptron (MLP) neural network for multimodal time-series data classification. Binarized versions of the 3-layers MLP and ResNet-20 are implemented on BiNMAC. The implementation results show that BiNMAC consumes 0.02 mJ and 3.8 mJ energy which is 13 times and 30 times lower than the implementation of standard non-binarized MLP and ResNet-20 on an equivalent predecessor platform. To compare the performance of the BiNMAC with other off-the-shelf platforms, the two networks are also implemented on the NVIDIA Jetson TX2 SoC (CPU+GPU). BiNMAC achieves 22 times and 78 times higher throughput and 23 times and 41 times lower energy consumption compared to TX2 SoC for the binarized MLP and ResNet-20, respectively.

Side-channel analysis techniques have been demonstrated for secret information extraction, vulnerability assessment and intrusion analysis. However, these techniques have not been applied to identify instructions running on a general purpose pipelined computing platform. In this work we identify instruction execution sequences on these platforms using side-channel power measurements. The technique uses a Principal Component Analysis (PCA) based model to generate multiple power-supply templates and a novel post-processing dynamic programming algorithm for optimal template matching. One unique aspect of this technique is that we take measurements on multiple power supply pins on the device, to increase the precision and accuracy. We apply our dynamic programming algorithm, to detect the sequence of execution clock cycles, on templates for single instructions that provides accuracy in the range of 69.2% to 87.5% for ten thousand observations, from individual power supply pins. We further augment this technique to generate multiple dictionaries for various length instructions and use data from multiple power supply pins to increases the accuracy in the range of 87% to 100%. Further, classification rates for instruction templates based on operand addressing mode and specific hardware used, range from 87% to 100% using as few as 10 principal components. Using our methodology, we can determine malicious insertions in a pre-determined code sequence with a 100% accuracy, as demonstrated in the results.

This paper presents novel integration options for passive inductor which include: motor-shaped rotational and motor-shaped rotor-less inductor for high speed motor drive system. The novel options have been designed and their performance is compared with the conventional EE core inductor using finite element analysis. It is observed that there is a significant reduction in total losses at fundamental frequency along with substantial reduction in the AC copper loss at 10, 15 and 20 kHz switching frequencies, when the proposed integrated options are utilized. For the motor-shaped rotational inductor, the total losses at fundamental frequency and AC copper loss at different switching frequencies are reduced by 26.1% and 73.8% (at different switching frequencies) respectively. There is a reduction in overall volume by 3.6%, but this comes with 11.7% increase in weight. For the motor-shaped rotor-less inductor, the total losses at fundamental frequency and AC copper loss at different switching frequencies are reduced by 10.4% and 73.8% (at different switching frequencies) respectively. There is a reduction in overall volume by 3.6% but this comes with 6.1% increase in weight. The proposed designs can share the cooling system of the motor thus, eliminating the requirement of separate cooling system.

This paper presents a novel approach to integrate the output filter inductor in permanent magnet synchronous motor (PMSM) drive system. The integrated output filter inductor is based on utilizing the motor magnetics as a filter inductance instead of introducing a separate filter inductor. Thus, eliminating added filter inductor losses and associated weight and volume. The vector controlled model, taking modulation and switching effect in to account, has been developed using MATLAB/Simulink tool for the proposed integrated output filter inductor. The currents obtained from MATLAB/Simulink model are then injected into the Finite Element model to validate the concept. The performance of the proposed and conventional system is analyzed in terms of mean electromagnetic torque, torque ripple, motor losses, inductor losses, weight and volume.

Evaluating and debugging solar panel-driven systems is a cumbersome process. The system must be deployed in the wild, software and hardware bugs identified remotely, and the development cycle must be repeated to build a robust system. Emulation platforms for solar panels offer a plausible remedy, however, existing systems have narrow operating range and are not portable. To address these shortcomings, we design, implement, and evaluate the SunaPlayer, a solar panel emulation platform that supports a wide operating current range (430 micro-amps to 1.89 amps) and voltage range (0.02 V to 9.8 V), and can be powered using batteries. SunaPlayer uses a high gain analog device, a PNP darlington transistor, a multi-scale driving and measurement circuit, and a novel state machine based proportional-integral-differential controller to build an accurate non-linear model of the solar panel. We have implemented a fully functional SunaPlayer prototype, and demonstrate that it can emulate a wide range of solar panels with high accuracy, low latency, high sensitivity, and low power consumption. The design methodology for the SunaPlayer can be used to build systems that model hard to emulate non-linear devices.

Tongue gestures are a key modality for augmentative and alternative communication in patients suffering from speech impairments and full-body paralysis. Systems for recognizing tongue gestures, however, are highly intrusive. They either rely on magnetic sensors built into dentures or artificial teeth deployed inside a patient's mouth or require contact with the skin using electromyography (EMG) sensors. Deploying sensors inside a patient's mouth can be uncomfortable for long-term use and contact-based sensors like EMG electrodes can cause skin abrasion. To address this problem, we present a novel contact-less sensor, called Tongue-n-Cheek, that captures tongue gestures using an array of micro-radars. The array of micro-radars act as proximity sensors and capture muscle movements when the patient performs the tongue gesture. Tongue-n-Cheek converts these movements into gestures using a novel signal processing algorithm. We demonstrate the efficacy of Tongue-n-Cheek and show that our system can reliably infer gestures with 95% accuracy and low latency.

Home automation and environmental control is a key ingredient of smart homes. While systems for home automation and control exist, there are few systems that interact with individuals suffering from paralysis, paresis, weakness and limited range of motion that are common sequels resulting from severe injuries such as stroke, brain injury, spinal cord injury and many chronic (guillian barre syndrome) and degenerative (amyotrophic lateral sclerosis) conditions. To address this problem, we present the design, implementation, and evaluation of Inviz, a low-cost gesture recognition system for paralysis patients that uses flexible textile-based capacitive sensor arrays for movement detection. The design of Inviz presents two novel research contributions. First, the system uses flexible textile-based capacitive arrays as proximity sensors that are minimally obtrusive and can be built into clothing for gesture and movement detection in patients with limited body motion. The proximity sensing obviates the need for touch-based gesture recognition that can cause skin abrasion in paralysis patients, and the array of capacitive sensors help provide better spatial resolution and noise cancellation. Second, Inviz uses a low-power hierarchical signal processing algorithm that breaks down computation into multiple low and high power tiers. The tiered approach provides maximal vigilance at minimal energy consumption. We have designed and implemented a fully functional prototype of Inviz and we evaluate it in the context of an end-to-end home automation system and show that it achieves high accuracy while maintaining low latency and low energy consumption.

Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test vectors cause increased switching as compared to functional operation resulting in increase in path delays. Test rejects due to excessive noise-induced failures during delay and transition testing negatively impacts yield. Hence there is a need to accurately characterize the resistive and inductive voltage drop caused by excessive switching. To our knowledge, inductive drop has been excluded to simplify noise analysis. In our previous work, we have presented a convolution-based dynamic method (herein referred to as PSANDE) to estimate both IR and Ldi/dt drop on small combinational and sequential circuits. In this paper we show that the effectiveness of the design partitioning technique makes the framework feasible for a larger design. Our dynamic approach involves selectively simulating only extracted switching logic which makes the run-time tractable as compared to prohibitive full-chip SPICE simulations. We also present data to show that PSANDE can accurately predict the power-supply noise due to clock tree switching. Data presented in this paper for power supply noise is based on a large ITC'99 sequential benchmark b17 circuit. with a maximum error of 8.2% in comparison to full-chip SPICE results.

The aftermath of a natural disaster is characterized by lack of a reliable medium for dissemination of information to survivors. The state-of-the-art emergency response systems rely on satellite radio-enabled devices, but survivors, unlike first responders, do not have access to such devices. To mitigate this problem, we present perpetuu, a solar-powered portable GIS microserver. The microserver node can be deployed in a disaster scene and can serve maps to survivors viewable on browsers of off-the-shelf mobile systems. The perpetuu nodes can form a wireless mesh to cover a large geographic region. A key innovation in the design of the perpetuu node is a tiered software and hardware architecture—the system combines a low-power micro-controller with a high-power micro-processor to provide a large spectrum of power states. perpetuu stays in its lowest power state most of the time, and it can in-vitro detect survivors using Wi-Fi sensing, and consequently wake up the higher-power tier to disseminate high-resolution maps on standard web browsers that provide directions to safe locations. The tiered design leverages hardware-assisted energy measurements and a wakeup controller to balance energy harvested from solar panels with energy consumed by the system. We evaluate perpetuu using measurements from our prototype and trace-based simulations, and show that it can function near-perpetually while serving maps to a large number of survivors.

Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when publishing the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby; it would draw practically nothing — just the leakage current. It was therefore a fact that CMOS circuits with increased standby power consumption were defective. In 1981 Mark W. Levi demonstrated the concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) in his ITC'1981 paper “CMOS is most Testable”. This paper kicked off a lot of research on IDDQ fault modeling, IDDQ defect detection capabilities, IDDQ and reliability, IDDQ efficiency. Much of that research happened in the late eighties — early nineties by “Chuck and Jerry”, exploring the benefits, followed by studies done by HP, IBM, TI, Philips, Alcatel, Ford Micro, … Since then IDDQ testing became synonym to current testing. Extensive research revealed the IDDQ capabilities. Despite its demonstrated defect detection capabilities and screening efficiency, it was not an easy way for IDDQ to make it to the production test floor. The initial lack of commercial available ATPG tools and suitable measurement solutions were the hurdles to take.

Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay caused by variations in power-supply voltage. This increase in delay can cause significant overkill during transition and delay testing. It is critical to account for this increase in delay during the ATPG process. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. To overcome this issue, our technique uses simulations of individual extracted paths and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for the C6288 ISCAS'85 benchmark circuit are presented. Our technique can also be applied to sequential circuits and simulation results demonstrating this are also presented.

Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to power supply noise. Running full-chip simulations on large designs to predict the noise is time consuming and expensive. Therefore, most existing techniques are based on statistical approaches. In this paper, we propose a current-based dynamic method to estimate power supply noise and use the framework to predict the increase in path delay caused by the variations in power supply voltage without carrying out a full-chip simulation. A convolution-based technique is used to compute the path delays where standalone paths are extracted and simulated. Experimental results reported for estimating noise using the ISCAS-85 benchmark circuit are within 10% of full-chip results. The delay predictions carried out on two other experimental designs using our technique closely match full-chip results with a maximum error of 2%.

OBJECTIVE: To use the semantic and structural properties in the Unified Medical Language System (UMLS) Metathesaurus to characterize and discover potential relationships. DESIGN: The UMLS integrates knowledge from several biomedical terminologies. This knowledge can be used to discover implicit semantic relationships between concepts. In this paper, the authors propose a problem-independent approach for discovering potential terminological relationships that employs semantic abstraction of indirect relationship paths to perform classification and analysis of network theoretical measures such as topological overlap, preferential attachment, graph partitioning, and number of indirect paths. Using different versions of the UMLS, the authors evaluate the proposed approach's ability to predict newly added relationships. MEASUREMENTS: Classification accuracy, precision-recall. RESULTS: Strong discriminative characteristics were observed with a semantic abstraction based classifier (classification accuracy of 91%), the average number of indirect paths, preferential attachment, and graph partitioning to identify potential relationships. The proposed relationship prediction algorithm resulted in 56% recall in top 10 results for new relationships added to subsequent versions of the UMLS between 2005 and 2007. CONCLUSIONS: The UMLS has sufficient knowledge to enable discovery of potential terminological relationships.

Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.

The vision of the Semantic Web is to reduce manual discovery and usage of Web resources (documents and services) and to allow software agents to automatically identify these Web resources, integrate them and execute them for achieving the intended goals of the user. Such a composed Web service may be represented as a workflow, called service flow. Current studies of Web services are not sufficient for automatic composition. This paper presents different types of compositional knowledge required for Web service discovery and composition: syntactic, semantic and pragmatic knowledge. As a proof of concept, we have implemented our framework in a cardiovascular domain which requires advanced service discovery and composition across heterogeneous platforms of multiple organizations. Within this framework, we describe (1) How to represent the compositional knowledge, which plays a role in service discovery and composition, in DAML-S; (2) How heterogeneous medical services intemperate in a composed medical service flow. (3) To solve this knowledge level integration, we build on an ontology integration method called SEMIO (Semantic Interoperability).

Web Services are emerging technologies that enable application-to-application communication and reuse of autonomous services over the Web. Recent efforts, OWLS, model the semantics of Web Services that includes the capabilities of the service, the service interaction protocol, and the actual messages for service exchanges. However, there is a need to automate discovery, selection and execution of OWL-S services. Further, a framework that meets the quality of service (QoS) requirements for ad hoc Internet based services is rarely provided. In this paper, we have proposed a rule-based framework, called SetnWebQ, which manages workflows composed of Semantic Web Services. SemWebQ is capable of conducting QoS-based adaptive selection as well as dynamic binding and execution of Web Services according to the semantics of workflow, thereby rendering a resilient and adaptive Web based service flow. A series of experiments performed on the SemWebQ with real Web Services have confirmed the effectiveness of proposed framework with respect to adaptive selection and execution of the Web Services in Web based workflows.

I/sub DDQ/ or steady state current testing has been extensively used in the industry as a mainstream defect detection and reliability screen. The background leakage current has increased significantly with the advent of ultra deep submicron technologies. The increased background leakage makes it difficult to use single threshold I/sub DDQ/ testing to differentiate defect-free chips from those with defects that draw small amount of currents. Several techniques that improve the resolution of I/sub DDQ/ testing have been proposed to replace the single threshold detection scheme. However, even these techniques are challenged to detect defects in the presence of leakage currents in excess of a few mA. All of these techniques use a single I/sub DDQ/ measurement per circuit configuration for detection and thus the scalability of these techniques is limited. Quiescent signal analysis (QSA) is a novel I/sub DDQ/ defect detection and diagnosis technique that uses I/sub DDQ/ measurements at multiple chip supply pads. Implicit in our methodology is a leakage calibration technique that scales the total leakage current over multiple simultaneous measurements. This helps in decreasing the background leakage component in individual measurements and thus increases the resolution of this technique to subtle defects. The effectiveness of this technique is demonstrated in This work using simulation experiments on portion of a production power grid. Predicted chip size and leakage values from the International Technology Roadmap for semiconductors (ITRS) are used in these experiments. The performance of the proposed technique is evaluated using three different intra-die process variation distribution models.

A technique for testing analog and mixed-signal linear circuit components based on their impulse response (IR) signatures is presented in This work. A simple DFT structure is proposed to enable the on-chip generation of the impulse response signatures from the corresponding step responses of the circuit components. The proposed technique circumvents the need to apply pseudorandom patterns and perform complex on-chip cross-correlation for IR generation. A set of post processing steps based on cross/auto-correlation are proposed to efficiently compare IR signatures. A statistical approach based on linear regression and outlier analysis is used for defect screening. A continuous-time active state variable filter benchmark circuit is used as the device-under-test as a means of validating this technique. The detection sensitivity for shorting and open resistive faults across various defect severity levels is analyzed. The detection results are compared and shown to be superior to a typical specification based test.

A wireless sensor network deployed in an area of interest is affected by variations in environmental conditions associated with that area. It must adapt to these variations in order to continue functioning as desired by the user. We present a novel, two-phase solution to the wireless sensor network adaptivity problem. In the first phase, nodes in the network, organized as clusters, execute an efficient algorithm to dynamically calibrate sensed data. Each node provides its current energy level and the state of each on-board sensor to a cluster-head. In the second phase, each cluster-head executes an efficient, ontology-driven algorithm to determine the future state of the network under existing conditions, based on information received from each sensor node. We describe an example application scenario to show how our two-phase solution can be employed to enable a real-world wireless sensor network to adapt itself to variations in environmental conditions.

In today's technologies, resistive shorting and open defects are becoming more predominant. Conventional fault models, and tools based on these models are becoming inadequate in addressing these defects resulting from new failure mechanisms. In prior works i/sub DDT/ testing techniques have been shown to detect resistive defects. However, in order to incorporate i/sub DDT/ based methods into production test flows, it is necessary to develop a fault simulation strategy to enable ATPG and fault coverage to be determined. To our knowledge, no practical technique exists to perform fault simulation for i/sub DDT/ based methods. At the heart of the difficulty of developing a fault simulation strategy is the analog nature of the test observable. In this paper we investigate a fault simulation model that partitions the task of simulating the CUT (chip under test) into linear and non-linear components. We also propose a path isolation strategy for core-logic as a means of reducing the computational complexity involved in deriving i/sub DDT/ signals in the non-linear portion. More specifically an Impulse Response based method is derived to eliminate the need for transient simulations of the entire CUT.

We compare implementations of Duprat and Muller's branching CORDIC and Phatak's double step branching (DSB)-CORDIC algorithms for sine and cosine evaluation. For reference we also report on classical CORDIC implementations for the same wordlengths. We have also implemented double stepping in the classical algorithm and report on the performance of this method. CORDIC evaluation of sine and cosine includes two parts, the zeroer and the rotator. We discuss implementation issues related to the minimization of the delay of each iteration of the algorithm (including delays for both the zeroer as well the rotator). We then examine hybrid methods that select the components from different algorithms (such as a DSB zeroer together with a classical rotator or vice versa).

Transient signal analysis (TSA) is a testing method that is based on the analysis of a set of V/sub DD/ transient waveforms measured simultaneously at each supply port. Defect detection is performed by applying linear regression analysis to the time or frequency domain representations of these signals. Chip-wide process variation effects introduce signal variations that are correlated across the individual power port measurements. In contrast, defects introduce uncorrelated local variations across these measurements that can be detected as anomalies in the cross-correlation profile derived (using regression analysis) from the power port measurements of defect-free chips. This paper focuses on the application of TSA to the detection of delay faults.

We discuss a circuit which measures and analyses power supply transients as defined in the test technique, Transient Signal Analysis (TSA). This circuit can replace the benchtop instrumentation and offline signal processing software used in previous work. The circuit accepts voltage transients as analog inputs from the Device-Under-Test (DUT), performs integration and outputs an analog value to the tester. The tester compares the output value to a predetermined threshold as a means of determining the pass/fail status of the DUT. This circuit is designed to simplify the hardware requirements of TSA.

A delay-fault testing strategy based on the analysis of power supply transient signals is presented. The method is an extension to a Go/No-Go device testing method called Transient Signal Analysis (TSA). TSA detects defects through the analysis of a set of power supply transient waveforms in the time or frequency domain, e.g., Fourier phase components. A recent extension to TSA demonstrated a correlation between the V/sub DDT/ Fourier phase components and path delays in defect-free devices. The method proposed here is able to detect increases in delay due to resistive shorting and open defects using a similar technique. In particular simulation results show that a delay defective device can be distinguished from a defect-free device through an anomaly in the Fourier phase correlation profile of the device.

The use of I/sub DDQ/ test as a defect reliability screen has been widely used to improve device quality. However, the increase in subthreshold leakage currents in deep submicron technologies has made it difficult to set an absolute pass/fail threshold. Recent work has focused on strategies that calibrate for process and/or technology-related variation effects. In this paper, a new I/sub DDQ/ technique is proposed that is based on an extension of a V/sub DDT/-based method called Transient Signal Analysis (TSA). The method, called Quiescent Signal Analysis or QSA, uses the I/sub DDQ/s measured at multiple supply pins as a means of localizing defects. Increases in I/sub DDQ/ due to a defect are regionalized by the resistive element of the supply grid. Therefore, each supply pin sources a unique fraction of the total I/sub DDQ/ drawn by the defect. The method analyzes the regional I/sub DDQ/s and "triangulates" the position of the defect to an (x,y) location in the layout. This information can be used in combination with fault dictionary-based techniques as a means of further resolving the defect's location.

Transient Signal Analysis (TSA) is a Go/No-Go device testing method that is based on the analysis of voltage transients at multiple test points. In this paper a technique based on an extension to TSA is presented that is able to predict critical path delay using data from non-critical (predictor) path tests. A characterization phase is performed a priori in which both predictor path and critical path delays are measured from a set of defect-free devices. The characterization data is used to define the relationship between the power supply transient signal data and the actual delays. Once established, prediction is performed during production test by simply re-analyzing the data from the predictor path Go/No-Go TSA tests, and therefore, no speed bin testing is required. Simulations on an 8-bit multiplier are used to demonstrate a linear relationship between a range of supply rail Fourier Phase harmonics and delay under various process models. The accuracy of the prediction is evaluated statistically against the measured delays from an additional set of critical path simulations.