The research of augmented reality physical tasks for human-computer collaboration is still an attractive dynamic research field. In recent years, AR Instruction supporting collaborative assembly has been developed, which can transfer graphic annotation between man and machine. However, there is little research on high precision manual assembly. This paper proposes a high-precision cognitive AR representation (M-AR) for manual operation guidance, which aims to transform a high-precision assembly relationship into a series of visual information to meet the user’s cognition of high-precision task intention. Using this representation, we conducted a within-subject case study to compare it with original AR representation (original AR) and low-precision cognitive AR representation. The results showed that there were significant differences in execution time and operation errors. The user’s subjective feedback also showed that M-AR supporting cognitive feedback can significantly improve a user’s cognitive experience in a physical task.

Research on Augmented Reality (AR)/Mixed Reality (MR) remote collaboration for physical tasks remains a compelling and dynamic area of study. AR systems have been developed which transmit virtual annotations between remote collaborators, but there has been little research on how haptic feedback can also be shared. In this paper, we present a Virtual Reality (VR)-Spatial Augmented Reality (SAR) remote collaborative system that provides haptic feedback with tangible interaction between a local worker and a remote expert helper. Using this system, we conducted a within-subject user study to compare two interfaces for remote collaboration between a local worker and expert helper, one with mid-air free drawing (MFD) and one with tangible physical drawing (TPD). The results showed that there were no significant differences with respect to performance time and operation errors. However, users felt that the TPD interface supporting passive haptic feedback could significantly improve the remote experts’ user experience in VR. Our research provides useful information on the way for gesture- and gaze-based multimodal interaction supporting haptic feedback in AR/MR remote collaboration on physical tasks.

Abstract This paper investigates the effect of using augmented reality (AR) annotations and two different gaze visualizations, head pointer (HP) and eye gaze (EG), in an AR system for remote collaboration on physical tasks. First, we developed a spatial AR remote collaboration platform that supports sharing the remote expert’s HP or EG cues. Then the prototype system was evaluated with a user study comparing three conditions for sharing non-verbal cues: (1) a cursor pointer (CP), (2) HP and (3) EG with respect to task performance, workload assessment and user experience. We found that there was a clear difference between these three conditions in the performance time but no significant difference between the HP and EG conditions. When considering the perceived collaboration quality, the HP/EG interface was statistically significantly higher than the CP interface, but there was no significant difference for workload assessment between these three conditions. We used low-cost head tracking for the HP cue and found that this served as an effective referential pointer. This implies that in some circumstances, HP could be a good proxy for EG in remote collaboration. Head pointing is more accessible and cheaper to use than more expensive eye-tracking hardware and paves the way for multi-modal interaction based on HP and gesture in AR remote collaboration.

Haptic guidance is an essential research topic of haptic interaction technology. In some conditions, haptic guidance devices could be better at assisting navigation. We developed Haptic Compass, a prototype with active vibrotactile feedback by attaching vibration motors to a cylinder-shaped physical object, to provide directional cues for haptic guidance. To validate the prototype, we conducted two user studies. The first study investigated if users could identify the vibrotactile feedback from the prototype. The results showed that participants could effectively recognize and judge the vibration direction. In the second study, we evaluated the task completion time and the movement error among the Visual-only, Haptic-Only and Haptic-Visual feedback conditions in a typical path-guiding task. We found that, together with visual feedback, haptic feedback could enhance task performance and user experience for direct path guidance. Performance of the two studies demonstrated that our prototype has the potential to be an alternative for applications where non-wearable haptic feedback is desired.

This paper investigates how two different unique gaze visualizations (the head pointer(HP), eye gaze(EG)) affect table-size physical tasks in Mixed Reality (MR) remote collaboration. We developed a remote collaborative MR Platform which supports sharing of the remote expert's HP and EG. The prototype was evaluated with a user study comparing two conditions: sharing HP and EG with respect to their effectiveness in the performance and quality of cooperation. There was a statistically significant difference between two conditions on the performance time, and HP is a good proxy for EG in remote collaboration.

Haptic feedback has shown its great value in HCI research and applications for enhancing user experiences. Simulating people's tactile sensations of virtual objects is currently a primary research target. Different from wearing motors on fingers or hands, we attached vibration motors on a physical object to simulate the augmented sense of collision with virtual objects to bare hands. We developed a novel sensor-based proof-of-concept prototype that distributes multiple vibration motors around a physical object and provides vibrational sensations from the collision direction through combinations of motors. Users can obtain augmented haptic feedback when manipulating the augmented physical object to interact with virtual objects in an AR environment. We first studied the influence of the number and input voltage of motors for a correct judgment of different directions to identify the design parameters of the prototype. Then we investigated the effect of introducing the prototype in a typical manipulation task in AR. We found the prototype was efficient for enhancing human performance and collision experience with virtual objects together with visual feedback.

Due to lack of effective model representation, current MBD models cannot perform well in manufacturing reuse. In this paper, a new multilevel structuralized MBD model for manufacturing reuse is presented to capture the abstract information, topological information and machining semantic information involved. Firstly, the machining features considered as the machining semantic carriers are recognized from the MBD model. Then, the coupled machining feature cluster is introduced to construct the greater granularity structural elements than the machining features. Finally, the MBD model is structuralized by reorganizing the machining features and the coupled machining feature clusters in a hierarchical way. In the experiment, an aircraft structural part is utilized to verify our approach for manufacturing reuse.

This paper describes a novel method for retrieving 3D models. Following the principle of compound-eye vision, the proposed method represents a 3D model as a spherical image, and discriminates different 3D models using their corresponding spherical images. Meanwhile, by borrowing the concept of the Scale-Invariant Feature Transform (SIFT) algorithm, we design a feature extraction algorithm, named Spherical-SIFT, for extracting the salient local features on spherical images. Moreover, the Bag-of-Features approach is employed so as to achieve efficient comparison of different 3D models. The experimental results show the superior performance of our method over pervious methods.

The representation of triangular mesh surface is proposed using spherical image. Surface signals like normals and curvatures are stored in spherical images using spherical parameterization and partition of the sphere. The generation depends on several geometric signals, not one single geometric signal. So its color reflects the properties of the triangular mesh surface more clearly. With simple arrays similar to 2D image, the spherical image can be post-processed easily using sophisticated image processing algorithms. Applications include segmentation, editing and model retrieval.

Radiation-induced transient errors have become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability metrics. We present a novel ldquonoise impact analysisrdquo methodology to evaluate the transient error effects in static CMOS digital circuits. With both the circuit, and the transient noise abstracted in the format of matrices, the circuit-noise interaction is modeled by a series of matrix transformations. During the transformation, factors that potentially affect the propagation & capture of transient errors are modeled as matrix operations. Finally, a ldquonoise capture ratiordquo is computed as the probability of a sequential element capturing transient noise inside the combinational logics, It is used as a measure of the transient noise effects in the circuit. Comparison with SPICE simulation demonstrates that our technique can accurately, yet quickly estimate the probability of transient errors causing observable error effects. The proposed methodology will greatly facilitate the economic design of robust nanometer circuits.

Single-event-upset (SEU) has become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability analysis. In this paper, a static "noise impact analysis" methodology is developed to estimate the circuit vulnerability. First, both the circuit elements and the transient noise are abstracted in the format of matrices. Then the circuit-noise interaction is modeled by a series of matrix transformations, which jointly considers three masking effects that can potentially prevent transient noise from causing observable errors. Finally, the error-resiliency of the sequential elements is considered in determining the impact of transient noise on the circuit. Experiment results demonstrate that our technique can accurately yet quickly estimate the circuit failure rate by comparing with HSPICE simulation. The proposed methodology has greatly facilitate the economic design of robust nanometer circuit.

Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to ensure reliable functioning of chips is to be able to analyze and identify the spots in the circuit which are susceptible to such effects (called “soft spots ” in this paper), and to make sure such soft spots are “hardened ” so as to resist multiple noise effects and soft errors. In this paper, we present a scalable soft spot analysis methodology to study the vulnerability of digital ICs exposed to nano-meter noise and transient soft errors. First, we define “softness ” as an important characteristic to gauge system vulnerability. Then several key factors affecting softness are examined. Finally an efficient Automatic Soft Spot Analyzer (ASSA) is developed to obtain the softness distribution which reflects the unbalanced noise-tolerant capability of different regions in a design. The proposed methodology provides guidelines to reduction of severe nano-meter noise effects caused by aggressive design in the premanufacturing phase, and guidelines to selective insertion of online protection schemes to achieve higher robustness. The quality of the proposed soft-spot analysis technique is validated by HSPICE simulation, and its scalability is demonstrated on a commercial embedded processor.

With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear drivers cannot be totally ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Based on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis.

For system-on-chips (SoC) using nanometer technologies, buses and long interconnects are susceptible to crosstalk defects that may lead to functional and timing failures. Testing for crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage of existing tests and facilitate the development of new crosstalk test methodologies, effective crosstalk-defect coverage-analysis techniques are needed. In this paper, we present an efficient high-level crosstalk-defect simulation methodology for interconnects dominated by capacitive coupling effects. A novel coupling defect-simulation model was developed and implemented in hardware description languages. The high-level crosstalk-defect simulation methodology was examined by SPICE simulations. Experimental results show the crosstalk defect simulation methodology efficiently provides high-fidelity defect-coverage results. The proposed methodology enables fast exploration and evaluation of different tests, leading to high-quality, low-cost manufacturing tests for crosstalk-induced ac failures.

As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk noise generated by coupling capacitances between wires. Test vectors that activate and propagate crosstalk noise effects are becoming an essential part of design verification and manufacturing test. However, deriving such vectors is a complex task. In this paper, we propose HyAC, a fast yet accurate hybrid ATPG method targeting multiple-aggressor induced crosstalk errors. Given a victim and a set of aggressors, the proposed ATPG method searches for test vectors to activate and propagate a crosstalk error for the victim. Due to logic constraints, it may not be possible to trigger all aggressors simultaneously. Therefore, firstly we use an implication graph (IG) that consists of logic variables and structural information to check for logic conflicts. If the current set of aggressors is not feasible, our algorithm automatically searches for the next-best subset of aggressors (resulting in the largest noise). After a set of feasible aggressors is identified, we use a modified PODEM [21] algorithm to search for test vectors. This hybrid structural SAT-based ATPG method inherits advantages from both Boolean– satisfiabilitity based methods and structural-based methods to achieve flexibility and efficiency. We demonstrate the accuracy, high quality, and run time efficiency of HyAC through experiments conducted on several benchmark circuits as well as a circuit from a commercial processor. 1.

Almost by definition, well-tuned digital circuits have a large number of equally critical paths, which form a so-called "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, model-to-hardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater.Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertainty-aware" mode has been implemented and applied to several high-performance microprocessor macros. Numerical results are included.

Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.

For system-on-chip (SoC) devices using deep submicron (DSM) technologies, the interconnects are becoming critical determinants for performance and reliability. Buses and long interconnects are susceptible to crosstalk defects and may lead to functional and timing failure. Hence, testing for crosstalk errors on interconnects and buses in a SoC has become critical. To facilitate development of new crosstalk test methodologies and to efficiently evaluate crosstalk defect coverage for existing tests there is a need for efficient crosstalk defect coverage analysis techniques. In this paper, we present an efficient high-level crosstalk defect simulation methodology. By using a novel high-level DSM error model for the interconnects, together with HDL models for the cores, our methodology enables fast crosstalk defect simulation to be conducted at high level. We validate the high-level interconnect DSM error model by comparing its outputs with HSPICE simulation results. The fast and accurate high-level crosstalk defect simulation methodology will enable evaluation and exploration of new crosstalk test techniques, as well as existing tests, leading to the development of a low-cost crosstalk test.

The effect of crosstalk errors is most significant in high-performance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test methodology is based on the Maximal Aggressor Fault Model [13], that enables testing of the interconnect with a linear number of test patterns. To enable self-testing of the interconnects, we have designed efficient on-chip test generators and error detectors to be embedded in necessary cores; while the test generators generate test vectors for crosstalk faults, the error detectors analyze the transmission of the test sequences received from the interconnects, and detect any transmission errors. We have also designed test controllers to initiate and manage test transactions by activating the appropriate test generators and error detectors, and having error diagnosis capability. We have developed, simulated, and synthesized parameterized HDL models of the self-test structures. We have applied the self-test methodology to test crosstalk defects in the buses of a DSP chip. Using a new high-level crosstalk simulation technique, we have validated the self-test methodology, including the self-test structures inserted in the DSP chip.

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.