Future 5G wireless systems will deploy massive MIMO systems with large numbers of transmit and receive antennas and novel RF transceiver architectures that admit RF beamforming. Such systems will need to be designed with built-in test and post-manufacture self-tuning capability for yield enhancement and in-field tuning. A key issue is the lack of observability into internal circuit nodes due to the convergence of multiple RF beamforming chains into a combined baseband signal and the need to decouple individual RF chain behaviors from combined baseband signals. A second problem is that of testing and tuning as many RF chains in parallel as possible across a diverse range of specifications and modes of operation (beam steering angles) using optimized test stimulus. The interdependence between phase shift and gain of phase-shifter/amplifier configurations complicates the latter. Also, in relation to SISO/MIMO omnidirectional systems, large numbers of tuning knobs are involved. To solve the above, we propose novel algorithms for parallel testing and tuning of massive MIMO beamforming systems. Machine learning assisted coarse tuning is first performed followed by a fine-tuning procedure utilizing gradient descent. Tuning for EVM and signal-to-interference ratio is performed under power constraints. Simulation results prove the viability of the proposed techniques.

This paper presents an AC magnetic field based High-Definition Personal Area Tracking (PAT) system. A low-power transmitter antenna acts as a reference for three tracker modules. One module, attached to the Head Mount Display (HMD), tracks the position and orientation of user's head and the other two hand-held modules act as an interface device (like virtual hands) in Virtual Reality. This precise, low power, low latency, non-line-of-sight system provides an easy-to-use human-computer interface. The system achieves a precision of 1 mm in position with 0.1 degree in orientation and an accuracy of 20 cm in position at a distance of 2 m from the antenna. The transmitter and the receiver consume 5 W and 0.4 W of power, respectively, providing 140 updates/sec with 11 ms of latency.

This paper presents real-time on-chip power and temperature sensors that provide fine-grained estimates for power consumption in systems-on-chip and also provide a concurrent temperature estimate for dynamic power and temperature management. This sensor occupies an area of 0.01 mm2in a 0.13-μm CMOS technology. With a simplified one-point calibration and a response time of 80 ns, it shows improvements in input dynamic range by ten times, response time by six times, and sensitivity by three times over previous such sensors. A compact low-power current reference with a 3-σmax TC of 127 ppm/°C and a line regulation of 1%/V is also presented, which is used in a replica-structure-based online calibration scheme, resulting in improved tolerance to variations in process, voltage, and temperature (PVT) and degradation due to supply noise as well as aging.

Recent developments in biomedical implants have increased the demand for on-chip power supplies. Switching power supplies provide high efficiency solution, which also serves in reducing the size of energy harvesting or energy storage devices. Hence, on-chip switching power supplies are ideal for implantable applications. However, they have the problem of higher ripple at the output than the conventional linear regulator due to the impractical values of on-chip components. In this paper, we present a new control methodology for on-chip switching power supply optimized for inductively powered implantable devices without any off-chip filtering components. The control methodology smoothens the transition between switching states based on pulse density modulation (PDM) feedback, in addition to an output voltage slope-limiting circuit. Simulated results of output ripple and efficiency based on 130nm RF-CMOS are shown. The control methodology reduce the ripple with minimal effect on power efficiency and without the need for any external filtering components.

An energy-efficient 4:1 multiplexer (MUX) operating at 40Gb/s using ETSPC logic is presented. For the first time, a single-phase clock digital-logic-based MUX operating with data rates above 20Gb/s is demonstrated. A new multifunctional 2:1 MUX cell with reduced number of transistors is proposed, and an efficiency of 21.5μW/Gb/s at 40Gb/s, gives the best power-efficiency reported. The MUX is designed in a 45nm SOI CMOS technology with 1V supply.

Energy conservation is essential in Wireless Sensor Networks (WSNs) because of limited energy in nodes' batteries. Collaborative beamforming uses multiple transmitters to form antenna arrays; the electromagnetic waves from these antenna arrays can create constructive interferences at the receiver and increase the transmission distance. Each transmitter can use lower power and save energy, since the energy consumption is spread over multiple transmitters. Each beamforming transmission requires multiple collaborative transmitters. Repetitively using the same transmitters will deplete their energy and create coverage holes in the sensing area. To prevent holes, energy should be balanced by using different transmitters. This article investigates the factors that can affect the energy consumption and network lifetime when using beamforming. We present an algorithm for selecting the transmitters in order to prolong the network lifetime. Compared with an existing beamforming transmitters scheduling algorithm, our algorithm doubles the network lifetime. When compared with direct transmission or multihop transmissions towards a receiver far away from the sensing area, our approach can increase the network's lifetime substantially.

For more than seventy years, all the development in digital electronics have been founded on Shannon's work based on the fact that Boolean logic operators, OR, AND and NOT, can form a computationally complete logic framework. We propose a new paradigm in logic circuit design using material implication logic operators, different from the traditional logic gates in implementation and operation. In this paper we present early evidences, with experimental silicon results, showing that this new logic framework significantly improves performance, power and speed, over an equivalent conventional-logic framework in CMOS. This new computing paradigm would enable the continuance of increasing computing functionality and performance with decreasing cost in silicon technologies.

We present a compact dual-modulus prescaler working at 50GHz without using inductors. A novel divider-by-2/3 in a reduced logic with minimum number of transistors is presented. For the first time, a single-phase clock digital-logic-based prescaler operating at frequencies in the mm-wave band is demonstrated. A power consumption of 130.2µW at 50GHz, gives the best power-efficiency reported. The prescaler is designed in a 45nm SOI CMOS technology with 1V supply.

We present a wide dynamic range, dual-mode low noise amplifier (LNA) operating in 0.8 to 6 GHz, which is suitable for a multi-band multi-standard front-end in a scaled CMOS technology and a low supply voltage operation. The digitally controlled high-sensitivity and high-linearity modes enable a low noise and a high linearity according to an input power to the LNA. In measurement, the LNA shows a power gain of 9.4 to 7.0 dB, a noise figure (NF) of 3.0 to 3.6 dB in high-sensitivity mode, and an input-referred 1-dB compression point (P1dB) of up to +4.2 dBm in high-linearity mode. The LNA draws 5.6 mA from a 1.1 V supply voltage in high-sensitivity mode and does not consume power in high-linearity mode. The design was implemented in 45 nm digital SOI CMOS technology.

Collaborative beamforming is a transmission technique by using multiple transmitters to form antenna arrays and creating highly directional beams to a distant receiver. Collaborative beamforming can enhance energy efficiency in wireless sensor networks. However, the same information needs to be shared among the transmitters in advance. As a result, communication among the transmitters is required; this consumes energy and shortens the lifetime of the sensor network. In this paper, we propose a procedure for data sharing when multiple sensing nodes and multiple transmitters are used and examine the energy consumption for beamforming. We show that beamforming is energy-efficient when the sensor nodes are deployed far away from the base station and the energy consumed for data sharing has negligible effects on the network's lifetime.

A fast and power efficient phase difference and frequency offset estimation technique for collaborative beamforming in a wireless sensor network is presented. Common radio blocks are used to implement the phase difference estimation technique and we present an analytical expression for the phase difference estimation accuracy in an AWGN channel. The analysis including the effect of noise and multipath on the estimation accuracy shows the effectiveness of the proposed estimation technique for collaborative beamforming applications.

Energy conservation is essential in wireless sensor networks (WSNs) because of limited energy in batteries. Collaborative beamforming uses multiple transmitters to form antenna arrays; the electromagnetic waves from these antenna arrays can create constructive interferences at the receiver and increase the transmission distance. Each transmitter can use lower power and save energy, since the energy consumption is spread over multiple transmitters. However, if the same nodes are always used for collaborative beamforming, these nodes would deplete their energy much sooner and this sensing area will no longer be monitored. To avoid this situation, energy consumption for collaborative beamforming needs to be balanced over the whole network by assigning the transmitters in turns. The transmitters in each round are selected by a scheduler and the energy carried in each node is balanced to increase the number of transmissions. We define the lifetime of a network as the number of transmissions until a certain percentage of the nodes depletes their energy. This paper proposes an algorithm to calculate energy-efficient schedules based on the remaining energy and the phase differences of their signals arriving at the receiver. Compared with an existing algorithm, our algorithm can extend the network lifetime by more than 60%.

Reducing energy consumption is critical for wireless sensor networks. The dominant factor is the energy for data transmission. Collaborative beamforming can save transmission energy by improving the directivity of electromagnetic waves so that the signal at the receiver is stronger. Compared with a single transmitter, collaborative beamforming spreads the long distance transmission energy over multiple transmitters. This balances the battery lifetime on individual nodes because each transmitter can use lower power. However, beamforming depends on proper coordination of phases among the participating sensor nodes. This requires communication among the sensor nodes and consumes energy. This paper investigates whether the transmission energy can be saved by using beamforming based on the number of nodes and the total size of data needed to transmit. We determine the minimum size of data to balance the communication overhead when given the total number of nodes.

We will demonstrate a new digital driving technique for AMOLED using ΔΣ modulation, which mitigates the TFT VT-shift issue with a simple 2-TFT-1-Cap pixel structure. It also solves the false image contour problem while achieving the same or better resolution and relaxed gate scan time compared with PWM. The system is implemented using a 2.2-inch QVGA AMOLED panel and FPGA.

This paper considers the problem of synchronization in frequency hopping systems. A simple digital signal processing block along with the existing RF circuits forms a phase detector that generates a signal corresponding to the phase difference between the hop timings of the local and received signals. The two hop-timing acquisition algorithms proposed in this paper - based on energy detection - utilize the phase detector and result in low-complexity implementations. In the first one, a simple cost function relying on the power sum definition estimates the hop timing. This estimator allows for only a limited acquisition range. Based on this study, we propose a hop-timing estimator with a full acquisition range which still maintains low-complexity. Furthermore, this paper analyzes the optimal threshold to detect the signal existence based on the maximum likelihood detection rule.

This paper presents a low power LC-VCO design using a direct cross-coupled cell biasing topology. In the proposed topology, the bias current mirror is directly connected to the gate of the cross-coupled cell that generates a negative resistance, and hence removes the voltage drop in the top- or tail-transistor used for current biasing. A capacitive degenerated buffer stage generates an extra negative resistance and relieves the current requirement for the VCO core, and further reduces the power consumption. The proposed topology is also insensitive to the power supply noise. An example 10 GHz VCO in 0.13 /spl mu/m CMOS technology drains only 0.6 mA from 1.2 V power supply. It shows 13.6% tuning range and -108 dBc/Hz phase noise at 1 MHz offset. For an operation under 0.8 V power supply with 0.45 mA current, the tuning range and phase noise degrade to 12.3% and -103dBc/Hz at 1 MHz offset respectively.