The aging population of european countries is becoming a social and economical stake. With age can come difficulties or disabilities to carry out daily life tasks, alone. Studies show that the number of the elderly people in France will be multiplied by two, within the next thirty years. To postpone as long as possible the hospitalization of dependent persons and allow them to live with dignity, researchers have been working on home automation, smart-homes and ambient assisted living. Nowadays, houses are still evolving and have, within them, equipments always more smarter. It is not uncommon to see electronic devices such as computer, connected tv and smart sensors: as many powerful resources not completely used. However, those untapped capacities could be used for person monitoring, video processing and other greedy algorithms, without adding any new specialized component. Thus it could ensure the quality of services required by the user and the dependability of its home automation system.

Nowadays, interaction with our surrounding environment has increased due to the presence of numerous devices that provide us with services. This is especially true in Smart Homes and can be of great help for the disabled people and the elderly that can no longer perform daily tasks they used to. However, in case of failure, corrective actions can be heavy to take, thus the need for the system to recover by itself and ensure service availability. Service availability is provided through service reconfiguration. This papers deals with service reconfiguration in smart homes. It presents a multi-level approach in which both off-line and on-line reconfiguration schemes are used to gradually recover from failed services. Static, effect-based, path and resource reconfiguration levels are described. They have been successfully implemented in the DANAH assistive system, which combines both navigation and service provision for smart homes.

This paper proposes a methodology for automatic control generation of conveying systems. Its purpose is to automate the development of discrete control programs in order to reduce costs. It is based on components to model controlled conveying systems. A component is a reusable element that includes several views including partial models. It is formalized referring to the notion of operations. Four views are delineated in this paper: operating part view, constraints view, topological view and control view. The control model of the workshop is built on these views. The procedure uses these partial models and refers to model transformation to provide an easy way to obtain source code compatible with the IEC 61131-3 standard. Tools allowing to implement the methodology are also presented, along with some applications.

Early performance feedback and design space exploration of complete field-programmable gate array (FPGA) designs are still time consuming tasks. This paper proposes an original methodology based on estimations to reduce the impact on design time. It promotes a hierarchical exploration to mitigate the complexity of the exploration process. Therefore, this work takes place before any design step, such as compilation or behavioral synthesis, where the specification is still provided as a C program. The goal is to provide early area and delay evaluations of many register-transfer level (RTL) implementations to prune the design space. Two main steps compose the flow: 1) a structural exploration step defines several RTL implementations, and 2) a physical mapping estimation step computes the mapping characteristics of these onto a given FPGA device. For the structural exploration, a simple yet realistic RTL model reduces the complexity and permits a fast definition of solutions. At this stage, it focuses on the computation parallelism and memory bandwidth. Advanced optimizations using for instance loop tiling, scalar replacement, or data layout are not considered. For the physical estimations, an analytical approach is used to provide fast and accurate area/delay tradeoffs. The paper also do not consider the impact of routing on critical paths or other optimizations. The reduction of the complexity allows the evaluation of key design alternatives, namely target device and parallelism that can also include the effect of resource allocation, bitwidth, or clock period. Due to this, a designer can quickly identify a reliable subset of solutions for which further refinement can be applied to enhance the relevance of the final architecture and reach a better use of FPGA resources, i.e., an optimal level of performance. Experiments performed with Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a two-dimensional Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations

This paper deals with the reconfiguration of flexible manufacturing systems. It presents a methodology that addresses the whole reaction loop toward failures. The major key point is the component notion that provides an easy way to get several models used in the monitoring supervision and control modules. A component is a reusable element that is composed of several views including partial models. It is formalized referring to the notion of operations and described using UML standard. Three views are delineated in this paper: monitoring view, supervision view and control view. Workshop models are built from these three views. The computation and the interactions of these models enable to get a relevant reaction for the reconfiguration process. Works concerning the detection, identification of down operations, the decision of a new configuration and the updating of control are presented.

Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural estimation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the target reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) components for a 2D DWT and a speech coder lead to an average error of about 10% for temporal values and 18% for area estimations.

The aim of this paper is to present an agent-based approach for the reconfiguration of transitic systems. These systems have to be reconfigured when unexpected events occurs (failures, integration of new resources, etc.). The reconfiguration procedure consists in new searching paths in the system enabling the different products to reach the appropriate resources in order to perform required production operations. The proposed reconfiguration procedure uses an extension of the ant colonies algorithms applied to the operational accessibility graph concept. The different entities of the system (resources, products, etc.) are implemented by means of the multi-agents paradigm. The approach is tested on an industrial conveyor with rollers.

In this paper, we address the problem of hardware interface design in a Codesign approach for real time Digital Signal Processing (DSP) applications. We focus on the allocation problem of necessary storage components needed for data communication between hardware-software components. First, we present a modeling style for I/O data exchanged between both components and we describe our generic model of the hardware interface. Second, we describe a formal technique to the necessary storage components allocation. Our design strategy starts from the hardware I/O transfer sequences computed by a high level synthesis tool, like GAUT (E. Martin et al., 1993). It incorporates some interface specification (I/O transfer order, timing constraints) obtained by any cosynthesis tool (such as that developed by P. H. Chon et al., 1995). The proposed allocation procedure assigns for each I/O data a time interval at which its transfer could occur. The results presented are based on FFT algorithms implemented on ASICs.

This paper relates experiences of algorithmic transformations in High Level Synthesis, in the area of acoustic echo cancellation. The processing and memory units are automatically designed for various equivalent LMS algorithms, in the FIR case, with important computational load. The results obtained with different filter lengths, give an accurate prototyping of new fast versions of the LMS algorithm. It also show that a theoretical arithmetic reduction must be correlated to the associated increase of memory requirements.