A multiprocessor which carries out multiple image recognition in parallel is proposed. It has been applied to an automatic routing algorithm for electronic CAD. The algorithm handles thousands of image planes. Each plane corresponds to the routing area of each net. Design rule check and path search are performed using image processing techniques for those planes. The multiprocessor architecture was evaluated by a software simulator and was found to achieve higher throughput, especially in the case of using a large number of processors.>

A technique is described for real-time solder joint inspection for printed wiring boards. It uses reflection on the specular solder surface projected by a straight-shaped light source (a straight fluorescent tube). For image processing, modified Hough transformation is adopted to approximate the image of the fluorescent tube reflected on a solder joint to a straight line. These processes are performed on special-purpose hardware to achieve video-rate processing. Experimental results have demonstrated sufficient detection capability.>

This paper describes a rule-based placement technique, which plays a key-role in the automatic layout system for Printed Wiring Boards. It is based on classification of bus-structures and other functional or structural features of PWB's.

This paper describes an automatic partitioning and placement system for CMOS gate arrays utilizing two different kinds of data: circuit structure and hierarchical design data. Characteristic circuit structures such as the bus structure and the iterative structure are automatically extracted and handled like single cells in the placement process. The partitioning process has employed two processes: one is the bottom-up extraction of these structures, and the other is the top-down process, which divides the given circuit into several subcircuits. Making use of the partitioning results, the placement program is also carried out by two-level processes: subcircuit-level placement and cell-level placement. Through experiments, it has been proved that the proposed technique is effective for attaining better layout results.

This paper describes a knowledge-based placement technique for printed wiring boards (PWB's).

This paper discusses a description technique for various kinds of processors. This technique is based on the Symbolic Functional Description Language, which allows logic designers to describe the behavior of hardwares at the register-transfer level in the top-down approach. The SFDL has been applied to the description of the internal behavior of a microprocessor and a data-flow processor.