A novel method is proposed for the adjustment and inspection of the large current sensors, which eliminates various difficulties arising from the large current handlings. The evaluation results of the proposed method are also discussed.

Reading life log is a type of techniques to automatically and unconsciously record people's reading intentions, interests and habits. Besides, it can also serve as various assistants in our daily life. In this paper, a reading-life log system is implemented by a head-mounted and unobtrusive video camera with a high resolution and a high shutter speed. We utilize DP matching, and propose a text-based frame mosaicing method to integrate multiple frames in a clip. The developed system is tested in the various environments indoor and outdoor. The experimental results show that our system can provide reliable outputs with respect to the most correct responses. The infrequent misregistration between lines also indicates the feasibility and validity of the text-based frame mosaicing.

Children with Down syndrome have a variety of symptoms including speech and swallowing disorders. To improve these symptoms, tongue training is thought to be beneficial. However, inducing children with Down syndrome to do such training is not easy because tongue training can be an unpleasant experience for children. In addition, with no supporting technology for such training, teachers and families around such children must make efforts to induce them to undergo the training. In this research, we develop an interactive tongue training system especially for children with Down syndrome using SITA (Simple Interface for Tongue motion Acquisition) system. In this paper, we describe in detail our preliminary evaluations of SITA, and present the results of user tests.

In this paper we formulate a dynamic model of a profit maximization problem for evaluating quantitatively how the policy of carbon tax and emissions trading would be effective to achieve the targeted reduction of the Kyoto Protocol. Furthermore, we evaluate the influence of carbon tax and emissions trading on the economy in industry in a long-term view. Keywords-global warming, carbon tax, emissions trading, dynamic model, Kyoto Protocol, economic impact

In this paper, we present a single-chip delta-sigma DAC and a class-D amplifier that utilizes internal antialias low-pass filters (LPF). The clock frequency of the delta-sigma modulator is lower than that of the delta-sigma DAC in order to reduce the power loss. The use of a closed-loop class-D amplifier with a balanced structure synchronized by a common-mode clock signal can drastically reduce aliasing noise and increase the LPF cutoff frequency. The chip area of the antialias LPF is reduced by one-hundredth. The test chip is fabricated by 0.35-/spl mu/m CMOS technology. The measured SNR, dynamic range, and THD of the test chip for audio applications are 94.7 dB, 95.0 dB, and 0.19 dB, respectively.

In large and high-speed LSI designs, the area and delay overhead of the design-for-test (DFT) circuit must be minimized while keeping sufficient testability. Partial scan is one of the techniques that can reduce the overhead of full scan. However, it is not simple to apply the partial scan method to large designs because of its long design turn-around-time (TAT) and pattern length. This paper presents an application of the partial scan method to a real LSI design. Several techniques have been introduced in order to effectively apply the method to the large high-end system LSI.

In this paper, we show a new blind identification algorithm which is based on second order statistics and exploits a single-input double-output (SIDO) model. It is suitable for a real-time processing system because of lower operation and high-speed convergence. The proposed blind identification algorithm is superior to conventional algorithms in view of simple structure and the uniqueness of solution. We also verify its efficiency by computer simulation.

A scientific parallel processor called the R256 has been developed. The R256 is composed of 16x16 processing elements, and has the outstanding features of a “distributed parallel network” as well as on IEEE 80-bit extended floating point computation ability. The computation accuracy, required by an exhaustive number of iterations in scientific computations, is resolved by the dedicated 80-bit VLSI processor, which was developed here for the R256. The innovative distributed parallel network was designed so as to effectively resolve heavy communication problems, which are found in applications based on the Monte Carlo simulation technique. The R256 network was very economical at a hardware cost of √N-folds (16 folds in this case) to that of an ideal full-crossbar switch, at the same time keeping the rates comparable to that of an ideal switch. The R256 demonstrates high performance of 2-GB/s data transfer rates and 500-MFLOPS computation rates on a semiconductor device simulation application.

A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The CAM-based backtracking is efficiently and quickly achieved by using CAM's sophisticated garbage collection function, which eliminates the need for stacks and additional operation cycles. In this machine, all Prolog execution can be simply controlled by a semantic information 'inference depth' without any address handling by storing all working information, binding and control information, in CAMs. This machine attains a performance of 100 KLIPS (kilo logical inference per second) on the deterministic append program in the interpretive mode, and also attains high performance in the nondeterministic program.>

A PE (Processing Element) LSI for a DTW (Dynamic Time Warping) linear array processor has been designed. In designing this LSI, major effort has been focused on achieving regular data-flow among adjacent PEs maintaining pipelined operation in the array. A three data channel structure, a triple buffer structure and sophisticated control schemes make it possible for the designed LSI to carry out MIMD (Multiple Instruction and Multiple Data streams) and continuous pipelined DTW processing in sync with regular pattern input. Due to the high speed real time operation, and the versatile function of this PE-LSI, a high performance linear array processor can be constructed using a small number of PEs. The high speed operation of LSI is pursuited to achieve real time processing. Continuous speech recognition with an approximate vocabulary of 1000 words can be achieved using only 20 to 30 of these PE-LSIs.

A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications. A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications.