Low-power artificial intelligence (AI) accelerators are being developed to support the battery-operated edge devices at a minimum expense of classification error. However, the testing of such large AI accelerators with traditional techniques is inefficient in achieving the required certifications for Autonomous Driving Assistant Systems (ISO 26262). ISO 26262 sets very stringent requirements on the testing time and fault coverage during the diagnosability of faults leading to system-level failures during in-field testing. This article proposes a test architecture for low-power AI accelerators by reusing the existing data paths for large AI accelerator arrays. As compared to the full scan-DFT, the proposed test architecture reduces the test time and peak test power, which enhances the reliability of the test responses. The proposed technique reduces 1) the switching power by 87%; 2) testing times by 72% on average for cases up to$32\times 32$; and 3) the peak power by 59%. Further, there is an average reduction in the area by 10% for the accelerator.

The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.

In[1], the corresponding author was incorrect. The correct corresponding author is Sungju Park.

The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods.

The semiconductor aging is one of the serious threats for the reliability of the system. This paper presents an efficient mechanism for predicting the aging effect. The captured data will be unloaded by shift operation, then verified through the aging monitoring operation. Especially the aging level of automotive semiconductor devices can be estimated by controlling the capture timing. Since the aging monitoring function is efficiently on and off during normal operation, power consumption can be reduced significantly compared with other approaches.

Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction - double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area and delay overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area and delay overhead.

Various studies propose that robots can be an effective tool for language teaching and learning. Especially they have been remarkably successful in elementary English classes [1][2][3][4]. The purpose of this study was to investigate some effects of a teaching assistant robot, Langbot, in elementary English classes in Korea. We adopted IROBIQ as Longbot for a pilot study.

This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a core-under-debug (CUD). The proposed approach supports debug of designs with multiple clock domains. It also supports collection of trace signatures to facilitate debug of long pattern sequences. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead. We also present simulation result to verify proper operation of the debug components.

This poster presents an efficient secure scan design based on a fake key to protect a secret key from scan-based side channel attack. This technique targeted for an SoC embedding an Advanced Encryption Standard (AES) core can be adopted without requiring any modification to the functional body of the IP core, thus overheads for area, timing, and power are negligible while preserving the compatibility with the IEEE1149.1 standard.

This research explores feasibility of using intellectual robots as a language instruction tool for young children. Since the intellectual robots have several sensors which can recognize status of the other parties, it can perform various bi-directional interaction strategies. This study verified how such bi-directional interaction using intellectual robots affects the improvement of linguistic ability. The subjects were 34 4-year-old children, 17 of whom were in the traditional media-assisted reading program, and 17 of whom were in the Robot-assisted reading program. The results indicated that the children in the robot-assisted groups improved significantly compared with media-assisted groups in linguistic ability (story making, understanding, word recognition, PPVT (Peabody Picture Vocabulary Test)). Furthermore, the benefits and limitations of using Intelligent Robot in linguistic education are discussed.

This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) bus system. Unfortunately, this architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based test access mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously, test application time on the expensive automatic test equipment (ATE) can be drastically reduced while preserving the compatibility with the ARM TIC.

This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments

This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, “$6n$” patterns are introduced to completely detect and diagnose both static and crosstalk faults, where “$n$” is the total number of interconnect nets. Then, more economic “$4n + 1$” patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.

In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in power dissipation and testabilities for benchmark circuits.

For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.

A new microcode-based BIST (built-in self test) circuitry for embedded memory components is proposed in this paper. The memory BIST implements march algorithms which are slightly modified by adopting DOF (degree of freedom) concept to detect ADOFs (address decoder open faults) on top of conventional stuck faults. Furthermore it is shown that the march BIST modified can capture a few NPSFs (neighborhood pattern sensitive faults) coupled with the cellular automata address generator and patterns. The microcode-based memory BIST proposed lends itself to performing different combinations of march and retention tests with less microcode storage than the other approaches.

OPKFDDs (Ordered Pseudo-Kronecker Functional Decision Diagrams) are one of ordered-DDs (Decision Diagrams) in which each node can take one of three decomposition types: Shannon, positive Davio and negative Davio. OPKFDDs provide representations of Boolean functions with smaller number of nodes than other DDs. Since an appropriate decomposition type has to be chosen for each node, the size of the representation is decided by the selection of the decomposition type as well as the variable ordering of the diagram. To overcome the huge search space for an optimal solution, a genetic algorithm is proposed to generate OPKFDDs with the minimal number of nodes with experimental results.

For supporting real-time interaction in distributed virtual environments (DVEs), it is common to replicate virtual world data at clients from the server. For efficient replication, two schemes are used together in general - prioritized transfer of objects and a caching and prefetching technique. Existing caching and prefetching approaches for DVEs exploit spatial relationship based on distances between a user and objects. However, spatial relationship fails to determine which types of objects are more important to an individual user, not reflecting user's interests. We propose a scalable data management scheme using user-based caching and prefetching exploiting the object's access priority generated from spatial distance and individual user's interest in objects in DVEs. We also further improve the cache hit rate by incorporating user's navigation behavior into the spatial relationship between a user and the objects in the cache. By combining the interest score and popularity score of an object with the spatial relationship, we improve the performance of caching and prefetching since the interaction locality between the user and objects are reflected in addition to spatial locality. The simulation results show that the proposed scheme outperforms the hit rate of existing caching and prefetching by 10% on average when the cache size is set to basic cache size, the size of expected number of objects included in the user's viewing range.

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores cannot be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore, 2log(N+2) interconnect test patterns are proposed for both static and delay testing.

To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. In this paper we analyzed and unified the strength of the techniques by structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flops but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for the most ISCAS89 benchmark circuits.

It is important to test the various kinds of interconnect faults between chips on a card/module.When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simpli ed.Various test generation algorithms have been developed for interconnect faults.A new interconnect test generation algorithm is introduced.It reduces the number of test patterns by half over present techniques.It also guarantees the complete diagnosis of mutiple interconnect faults.

Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.

The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults. >