Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this work, we present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. We then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations. We show that our approach can eliminate over 80% of the yield losses under medium level of variations, while incurring less than 1% per-access energy overhead on average and less than 4.5% area overhead.

We have constructed a FPGA-based “early neural circuit simulator” to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use tactile input from their whiskers to extract object features such as size and shape. We use the simulator to examine the plausibility of the hypothesis that neural circuits in the rat’s brain compute gradients of radial distance across the whisker array to make predictions about the environment. This prediction could be a component of a feed-forward signal that guides the navigation behavior of the rat. The use of a FPGA is highly suitable for such an application, because the computation involved in this system is a massively parallel problem. For our applications, we determined that a Cyclone II FPGA could simulate up to 14 neurons in parallel in just 265 ns achieving a 386-fold speedup over the software implementation of the same model.

Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could determine whether their users are satisfied, they could provide higher efficiency; improved reliability, reduced power consumption, increased security, and a better user experience. A major reason for this limitation is their input devices. Specifically, the traditional input devices (e.g., the mouse and keyboard) provide limited information about the user. In this paper, we make a case for the addition of new biometric input devices for providing the computer information about the userpsilas physiological traits. We explore three biometric devices as potential sensors: an eye tracker, a galvanic skin response (GSR) sensor, and force sensors. We first present two user studies that explore the link between the sensor readings and user satisfaction when the performance of the processor is varied as a video game is being played. In the first study, we drastically drop the processor clock frequency at a set point in the game. In the second study, we set the clock frequency to randomly-selected levels during game play. Both studies show that there are significant changes in human physiological traits as performance decreases. More importantly, we show that physiological changes correlate strongly to the satisfaction levels reported by the users. Based upon these observations, we construct a Physiological Traits-based Power-management (PTP) system that can be applied to existing dynamic voltage and frequency scaling (DVFS) schemes. We apply PTP to a typical CPU-utilization-based adaptive DVFS policy and evaluate our scheme using a third user study. An aggressive version of our PTP scheme reduces the total system power consumption of a laptop by up to 33.3% for an application averaged across users (18.1% averaged across three applications), while a conservative version reduces the total system power consumption by up to 25.6% across users (11.4% averaged across three applications).