Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized.The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.

There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad's positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming(SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage.

This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.

In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix Gswhich is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%–32% reduction in power network area, compared with the results from modern commercial PG synthesizer.