Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ji Young Park

dblp:95/170 · DBLP profile ↗
← Back
5ranked-venue papers
0as first author
0since 2021 · last 2015
0000-0003-4087-8494ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4Human-computer interaction and ubiquitous computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Human-computer interaction and pervasive computing
1 paper
Learning and educational technologies · 100%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Parallel and multicore computing · 67% Memory systems · 23% Processor architecture and microarchitecture · 10%
Software engineering, system software, and programming languages
2 papers
Compilers and program optimization · 100%

Topics — the 6 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Learning and educational technologies › informal learning
museum exhibits
0.212015
Trap it!: A Playful Human-Biology Interaction for a Museum Installation · CHI 2015
Parallel and multicore computing
parallel programming runtimes
0.112008
A portable runtime interface for multi-level memory hierarchies · PPoPP 2008
Compilers and program optimization › memory optimization
memory hierarchy optimization
0.112006
Sequoia: programming the memory hierarchy · SC 2006
Parallel and multicore computing
parallel programming models
0.112006
Sequoia: programming the memory hierarchy · SC 2006
Memory systems
data movement
0.012008
A portable runtime interface for multi-level memory hierarchies · PPoPP 2008
Memory systems
memory hierarchy
0.012008
A portable runtime interface for multi-level memory hierarchies · PPoPP 2008

Methods — techniques the papers use, named apart from their topics

user study · 0.2touchscreen interaction · 0.2light projection · 0.2compiler scheduling · 0.1bulk operation manipulation · 0.1runtime composition · 0.1compiler target interface · 0.1
YearPublicationVenuePosition
2015 Trap it!: A Playful Human-Biology Interaction for a Museum Installation
abstract
We developed Trap it!, a human-biology interaction (HBI) medium encompassing a touchscreen interface, microscopy, and light projection. Users can interact with living cells by drawing on a touchscreen displaying the microscope view of the cells. These drawings are projected onto the microscopy field as light patterns, prompting observable movement in phototactic responses. The system design enables stable and robust HBI and a wide variety of programmed activities (art, games, and experiments). We investigated its affordances as an exhibit in a science museum in both facilitated and unfacilitated contexts. Overall, it had a low barrier of entry and fostered rich communication among visitors. Visitors were particularly excited upon realizing that the interaction involved real organisms, an understanding that was facilitated by the eyepiece on the physical system. With the results from user study, we provide our observations, insights and guidelines for designing HBI as a permanent museum exhibit.
Seung Ah Lee, Engin Bumbacher, Alice M. Chung, Nate Cira, Byron Walker, Ji Young Park, Barry Starr, Paulo Blikstein, Ingmar H. Riedel-Kruse
CHI6
2008 A tuning framework for software-managed memory hierarchies
abstract
Achieving good performance on a modern machine with a multi-level memory hierarchy, and in particular on a machine with software-managed memories, requires precise tuning of programs to the machine's particular characteristics. A large program on a multi-level machine can easily expose tens or hundreds of inter-dependent parameters which require tuning, and manually searching the resultant large, non-linear space of program parameters is a tedious process of trial-and-error. In this paper we present a general framework for automatically tuning general applications to machines with software-managed memory hierarchies. We evaluate our framework by measuring the performance of benchmarks that are tuned for a range of machines with different memory hierarchy configurations: a cluster of Intel P4 Xeon processors, a single Cell processor, and a cluster of Sony Playstation3's.
Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally
PACT2
2008 A portable runtime interface for multi-level memory hierarchies
abstract
We present a platform independent runtime interface for moving data and computation through parallel machines with multi-level memory hierarchies. We show that this interface can be used as a compiler target and can be implemented easily and efficiently on a variety of platforms. The interface design allows us to compose multiple runtimes, achieving portability across machines with multiple memory levels. We demonstrate portability of programs across machines with two memory levels with runtime implementations for multi-core/SMP machines, the STI Cell Broadband Engine, a distributed memory cluster, and disk systems. We also demonstrate portability across machines with multiple memory levels by composing runtimes and running on a cluster of SMP nodes, out-of-core algorithms on a Sony Playstation 3 pulling data from disk, and a cluster of Sony Playstation 3's. With this uniform interface, we achieve good performance for our applications and maximize bandwidth and computational resources on these system configurations.
Mike Houston, Ji Young Park, Manman Ren, Timothy J. Knight, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
PPoPP2
2007 Compilation for explicitly managed memory hierarchies
abstract
We present a compiler for machines with an explicitly managed memory hierarchy and suggest that a primary role of any compiler for such architectures is to manipulate and schedule a hierarchy of bulk operations at varying scales of the application and of the machine. We evaluate the performance of our compiler using several benchmarks running on a Cell processor.
Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
PPoPP2
2006 Sequoia: programming the memory hierarchy
abstract
We present Sequoia, a programming language designed to facilitate the development of memory hierarchy aware parallel programs that remain portable across modern machines featuring different memory hierarchy configurations. Sequoia abstractly exposes hierarchical memory in the programming model and provides language mechanisms to describe communication vertically through the machine and to localize computation to particular memory locations within it. We have implemented a complete programming system, including a compiler and runtime systems for Cell processor-based blade systems and distributed memory clusters, and demonstrate efficient performance running Sequoia programs on both of these platforms.
Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan
SC6